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Platform-independent core collection
Commit 37acae1a authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch 'tom-mr-genrams-improvements' into 'proposed_master' 

Genrams improvements

See merge request !25
parents 074d4468 bca4cdf2
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Showing with 148 additions and 45 deletions
modules/genrams/altera/generic_dpram.vhd
View file @ 37acae1a
......@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2011-01-25
-- Last update: 2013-03-04
-- Last update: 2022-07-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -44,7 +44,9 @@ entity generic_dpram is
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_fail_if_file_not_found : boolean := true; -- dummy (exists in Xilinx/generic)
g_dual_clock : boolean := true);
g_dual_clock : boolean := true;
g_implementation_hint : string := "auto"
);
port(
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
......
modules/genrams/altera/generic_dpram_mixed.vhd
View file @ 37acae1a
......@@ -6,7 +6,7 @@
-- Author : C. Prados
-- Company : GSI
-- Created : 2014-08-25
-- Last update:
-- Last update: 2022-07-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -38,7 +38,9 @@ entity generic_dpram_mixed is
g_size : natural;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
g_dual_clock : boolean := true;
g_implementation_hint : string := "auto"
);
port(
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
......
modules/genrams/altera/generic_simple_dpram.vhd
View file @ 37acae1a
......@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-03-04
-- Last update: 2013-03-04
-- Last update: 2022-07-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -38,7 +38,8 @@ entity generic_simple_dpram is
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
g_dual_clock : boolean := true;
g_implementation_hint : string := "auto");
port(
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
......
modules/genrams/altera/generic_spram.vhd
View file @ 37acae1a
......@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2011-01-25
-- Last update: 2013-03-04
-- Last update: 2022-07-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -39,7 +39,8 @@ entity generic_spram is
g_size : natural := 1024;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "");
g_init_file : string := "";
g_implementation_hint : string := "auto");
port(
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
......
modules/genrams/common/inferred_async_fifo.vhd
View file @ 37acae1a
......@@ -53,8 +53,9 @@ entity inferred_async_fifo is
g_with_wr_count : boolean := FALSE;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
g_almost_full_threshold : integer; -- threshold for almost full flag
g_memory_implementation_hint : string := "auto");
port (
rst_n_i : in std_logic := '1';
......@@ -116,11 +117,24 @@ architecture syn of inferred_async_fifo is
bin_x, gray_x : t_counter;
end record;
constant c_counters_reset_value : t_counter_block :=
( bin => (others => '0'),
bin_next => (others => '0'),
gray => (others => '0'),
gray_next => (others => '0'),
bin_x => (others => '0'),
gray_x => (others => '0') );
type t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
signal mem : t_mem_type := (others => (others => '0'));
signal rcb, wcb : t_counter_block := (others =>(others => '0'));
attribute ram_type : string;
attribute ram_type of mem : signal is g_memory_implementation_hint;
signal rcb, wcb : t_counter_block := c_counters_reset_value;
signal full_int, empty_int : std_logic;
signal almost_full_int, almost_empty_int : std_logic;
signal going_full : std_logic;
......
modules/genrams/common/inferred_async_fifo_dual_rst.vhd
View file @ 37acae1a
......@@ -50,7 +50,8 @@ entity inferred_async_fifo_dual_rst is
g_with_wr_almost_full : boolean := FALSE;
g_with_wr_count : boolean := FALSE;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer);
g_almost_full_threshold : integer;
g_memory_implementation_hint : string := "auto");
port (
-- write port
rst_wr_n_i : in std_logic := '1';
......@@ -111,6 +112,9 @@ architecture arch of inferred_async_fifo_dual_rst is
signal rcb, wcb : t_counter_block := (others =>(others => '0'));
attribute ram_type : string;
attribute ram_type of mem : signal is g_memory_implementation_hint;
signal full_int, empty_int : std_logic;
signal almost_full_int, almost_empty_int : std_logic;
signal going_full : std_logic;
......
modules/genrams/common/inferred_sync_fifo.vhd
View file @ 37acae1a
......@@ -54,7 +54,9 @@ entity inferred_sync_fifo is
g_almost_empty_threshold : integer := 0; -- threshold for almost empty flag
g_almost_full_threshold : integer := 0; -- threshold for almost full flag
g_register_flag_outputs : boolean := true
g_register_flag_outputs : boolean := true;
g_memory_implementation_hint : string := "auto"
);
port (
......@@ -105,7 +107,8 @@ begin -- syn
g_size => g_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_dual_clock => false)
g_dual_clock => false,
g_implementation_hint => g_memory_implementation_hint)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
......
modules/genrams/generic/generic_async_fifo.vhd
View file @ 37acae1a
......@@ -53,7 +53,9 @@ entity generic_async_fifo is
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
g_almost_full_threshold : integer; -- threshold for almost full flag
g_memory_implementation_hint : string := "auto"
);
port (
......@@ -104,7 +106,9 @@ architecture syn of generic_async_fifo is
g_with_wr_almost_full : boolean;
g_with_wr_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer);
g_almost_full_threshold : integer;
g_memory_implementation_hint : string
);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
......@@ -144,7 +148,8 @@ begin -- syn
g_with_wr_almost_full => g_with_wr_almost_full,
g_with_wr_count => g_with_wr_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold)
g_almost_full_threshold => g_almost_full_threshold,
g_memory_implementation_hint => g_memory_implementation_hint )
port map (
rst_n_i => rst_n_i,
clk_wr_i => clk_wr_i,
......
modules/genrams/generic/generic_async_fifo_dual_rst.vhd
View file @ 37acae1a
......@@ -50,7 +50,8 @@ entity generic_async_fifo_dual_rst is
g_with_wr_almost_full : boolean := FALSE;
g_with_wr_count : boolean := FALSE;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
g_almost_full_threshold : integer := 0;
g_memory_implementation_hint : string := "auto" );
port (
-- write port
rst_wr_n_i : in std_logic := '1';
......@@ -96,7 +97,8 @@ begin -- arch
g_with_wr_almost_full => g_with_wr_almost_full,
g_with_wr_count => g_with_wr_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold)
g_almost_full_threshold => g_almost_full_threshold,
g_memory_implementation_hint => g_memory_implementation_hint )
port map (
rst_wr_n_i => rst_wr_n_i,
clk_wr_i => clk_wr_i,
......
modules/genrams/generic/generic_sync_fifo.vhd
View file @ 37acae1a
......@@ -53,7 +53,8 @@ entity generic_sync_fifo is
g_almost_empty_threshold : integer := 0; -- threshold for almost empty flag
g_almost_full_threshold : integer := 0; -- threshold for almost full flag
g_register_flag_outputs : boolean := true
g_register_flag_outputs : boolean := true;
g_memory_implementation_hint : string := "auto"
);
port (
......@@ -90,7 +91,8 @@ architecture syn of generic_sync_fifo is
g_with_count : boolean;
g_almost_empty_threshold : integer;
g_almost_full_threshold : integer;
g_register_flag_outputs : boolean);
g_register_flag_outputs : boolean;
g_memory_implementation_hint : string);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
......@@ -120,8 +122,8 @@ begin -- syn
g_with_count => g_with_count,
g_almost_empty_threshold => g_almost_empty_threshold,
g_almost_full_threshold => g_almost_full_threshold,
g_register_flag_outputs => g_register_flag_outputs)
g_register_flag_outputs => g_register_flag_outputs,
g_memory_implementation_hint => g_memory_implementation_hint )
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
......
modules/genrams/genram_pkg.vhd
View file @ 37acae1a
......@@ -48,7 +48,8 @@ package genram_pkg is
g_size : natural;
g_with_byte_enable : boolean := false;
g_init_file : string := "none";
g_addr_conflict_resolution : string := "dont_care") ;
g_addr_conflict_resolution : string := "dont_care";
g_implementation_hint : string := "auto") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
......@@ -66,7 +67,9 @@ package genram_pkg is
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
g_dual_clock : boolean := true;
g_implementation_hint : string := "auto"
);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
......@@ -87,7 +90,9 @@ package genram_pkg is
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_fail_if_file_not_found : boolean := true;
g_dual_clock : boolean := true);
g_dual_clock : boolean := true;
g_implementation_hint : string := "auto"
);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
......@@ -111,7 +116,9 @@ package genram_pkg is
g_size : natural;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_dual_clock : boolean := true);
g_dual_clock : boolean := true;
g_implementation_hint : string := "auto"
);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
......@@ -144,7 +151,8 @@ package genram_pkg is
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
g_almost_full_threshold : integer := 0;
g_memory_implementation_hint : string := "auto");
port (
rst_wr_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
......@@ -182,7 +190,9 @@ package genram_pkg is
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
g_almost_full_threshold : integer := 0;
g_memory_implementation_hint : string := "auto"
);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
......@@ -217,7 +227,9 @@ package genram_pkg is
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0;
g_register_flag_outputs : boolean := true);
g_register_flag_outputs : boolean := true;
g_memory_implementation_hint : string := "auto"
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
......@@ -248,6 +260,29 @@ package genram_pkg is
q_valid_o : out std_logic
);
end component;
component generic_dpram_split is
generic (
g_size : natural;
g_init_file : string := "none";
g_addr_conflict_resolution : string := "dont_care";
g_fail_if_file_not_found : boolean := true;
g_implementation_hint : string := "auto"
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
bwea_i : in std_logic_vector(3 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(31 downto 0);
qa_o : out std_logic_vector(31 downto 0);
bweb_i : in std_logic_vector(3 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(31 downto 0);
qb_o : out std_logic_vector(31 downto 0));
end component generic_dpram_split;
end genram_pkg;
......
modules/genrams/xilinx/generic_dpram.vhd
View file @ 37acae1a
......@@ -49,7 +49,8 @@ entity generic_dpram is
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true;
g_fail_if_file_not_found : boolean := true
g_fail_if_file_not_found : boolean := true;
g_implementation_hint : string := "auto"
);
port (
......@@ -89,7 +90,9 @@ architecture syn of generic_dpram is
g_size : natural;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_fail_if_file_not_found : boolean := true);
g_fail_if_file_not_found : boolean := true;
g_implementation_hint : string := "auto"
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
......@@ -112,7 +115,9 @@ architecture syn of generic_dpram is
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_fail_if_file_not_found : boolean);
g_fail_if_file_not_found : boolean;
g_implementation_hint : string
);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
......@@ -135,7 +140,9 @@ architecture syn of generic_dpram is
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_fail_if_file_not_found : boolean);
g_fail_if_file_not_found : boolean;
g_implementation_hint : string
);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
......@@ -167,7 +174,8 @@ begin
g_size => g_size,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_fail_if_file_not_found => g_fail_if_file_not_found)
g_fail_if_file_not_found => g_fail_if_file_not_found,
g_implementation_hint => g_implementation_hint)
port map(
rst_n_i => rst_n_i,
clk_i => clka_i,
......@@ -191,7 +199,8 @@ begin
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_fail_if_file_not_found => g_fail_if_file_not_found)
g_fail_if_file_not_found => g_fail_if_file_not_found,
g_implementation_hint => g_implementation_hint)
port map (
rst_n_i => rst_n_i,
clk_i => clka_i,
......@@ -217,7 +226,8 @@ begin
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_fail_if_file_not_found => g_fail_if_file_not_found)
g_fail_if_file_not_found => g_fail_if_file_not_found,
g_implementation_hint => g_implementation_hint)
port map (
rst_n_i => rst_n_i,
clka_i => clka_i,
......
modules/genrams/xilinx/generic_dpram_dualclock.vhd
View file @ 37acae1a
......@@ -48,7 +48,8 @@ entity generic_dpram_dualclock is
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
g_fail_if_file_not_found : boolean := true;
g_implementation_hint : string := "auto"
);
port (
......@@ -122,6 +123,9 @@ architecture syn of generic_dpram_dualclock is
shared variable ram : t_ram_type := f_file_to_ramtype;
attribute ram_type : string;
attribute ram_type of ram : variable is g_implementation_hint;
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
......
modules/genrams/xilinx/generic_dpram_sameclock.vhd
View file @ 37acae1a
......@@ -47,7 +47,8 @@ entity generic_dpram_sameclock is
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true
g_fail_if_file_not_found : boolean := true;
g_implementation_hint : string := "auto"
);
port (
......@@ -122,6 +123,9 @@ architecture syn of generic_dpram_sameclock is
shared variable ram : t_ram_type := f_file_to_ramtype;
attribute ram_type : string;
attribute ram_type of ram : variable is g_implementation_hint;
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
......
modules/genrams/xilinx/generic_dpram_split.vhd
View file @ 37acae1a
......@@ -61,7 +61,8 @@ entity generic_dpram_split is
g_size : natural := 16384;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_fail_if_file_not_found : boolean := true);
g_fail_if_file_not_found : boolean := true;
g_implementation_hint : string := "auto");
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
......@@ -112,6 +113,12 @@ architecture syn of generic_dpram_split is
shared variable ram2 : t_split_ram := f_file_to_ramtype(2);
shared variable ram3 : t_split_ram := f_file_to_ramtype(3);
attribute ram_type : string;
attribute ram_type of ram0 : variable is g_implementation_hint;
attribute ram_type of ram1 : variable is g_implementation_hint;
attribute ram_type of ram2 : variable is g_implementation_hint;
attribute ram_type of ram3 : variable is g_implementation_hint;
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
signal wea_rep : std_logic_vector(c_num_bytes-1 downto 0);
......
modules/genrams/xilinx/generic_simple_dpram.vhd
View file @ 37acae1a
......@@ -6,7 +6,7 @@
-- Author : Wesley W. Terpstra
-- Company : GSI
-- Created : 2013-03-04
-- Last update: 2013-10-30
-- Last update: 2022-07-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -58,7 +58,8 @@ entity generic_simple_dpram is
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean := true;
g_fail_if_file_not_found : boolean := true
g_fail_if_file_not_found : boolean := true;
g_implementation_hint : string := "auto"
);
port (
......@@ -93,7 +94,8 @@ begin
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_dual_clock => g_dual_clock)
g_dual_clock => g_dual_clock,
g_implementation_hint => g_implementation_hint )
port map(
rst_n_i => rst_n_i,
clka_i => clka_i,
......
modules/genrams/xilinx/generic_spram.vhd
View file @ 37acae1a
......@@ -19,7 +19,9 @@ entity generic_spram is
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
-- or "write_first" (write-then-read)
g_addr_conflict_resolution : string := "write_first";
g_init_file : string := ""
g_init_file : string := "";
g_implementation_hint : string := "auto"
);
port (
......@@ -59,7 +61,10 @@ architecture syn of generic_spram is
signal s_ram_in : std_logic_vector(g_data_width-1 downto 0);
signal s_ram_out : std_logic_vector(g_data_width-1 downto 0);
attribute ram_type : string;
attribute ram_type of ram : signal is g_implementation_hint;
begin
assert (g_init_file = "" or g_init_file = "none")
......
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