radtol/secded: add a testbench for secded_32b_pkg

6df8f915 · Tristan Gingold · 4f4faa78 · 6df8f915 · 6df8f915 · 6df8f915
Commit 6df8f915 authored Dec 03, 2021 by Tristan Gingold
Showing with 80 additions and 16 deletions

secded_32b_pkg.vhd modules/radtol/secded_32b_pkg.vhd +18 -15

secded_ecc.vhd modules/radtol/secded_ecc.vhd +1 -1

tb_secded_32b_pkg.vhd testbench/radtol/tb_secded_32b_pkg.vhd +61 -0

No files found.
--- a/modules/radtol/secded_32b_pkg.vhd
+++ b/modules/radtol/secded_32b_pkg.vhd
@@ -30,14 +30,21 @@ package secded_32b_pkg is
  subtype ecc_word_t is std_logic_vector (6 downto 0);

  --  Compute the ECC bits for DATA.
+  --  The ECC is a xor of some DATA bits.
  function f_calc_ecc (data : data_word_t) return ecc_word_t;

+  --  SYNDROME is the xor of read ECC and recomputed ECC.
+  --  The xor should be 0, except in case of errors.
+  --  Return '1' if there is a difference (so if SYNDROME is not 0)
  function f_ecc_errors (syndrome : ecc_word_t) return std_logic;

+  --  Return '1' if only one bit of SYNDROME is 1, ie if there is only one error.
+  --  (in that case it could be fixed).
  function f_ecc_one_error (syndrome : ecc_word_t) return std_logic;

  function f_fix_error (syndrome : ecc_word_t;
-                        data : std_logic_vector (38 downto 0)) return std_logic_vector;
+                        ecc : ecc_word_t;
+                        data : data_word_t) return std_logic_vector;
 end secded_32b_pkg;

 package body secded_32b_pkg is
@@ -98,12 +105,15 @@ package body secded_32b_pkg is
  end f_ecc_one_error;

  function f_fix_error (syndrome : ecc_word_t;
-                        data     : std_logic_vector (38 downto 0)) return std_logic_vector
+                        ecc : ecc_word_t;
+                        data : data_word_t) return std_logic_vector
  is
-    variable result         : std_logic_vector (31 downto 0) := (others => '1');
-    variable corrected_word : std_logic_vector (38 downto 0);
+    variable result : data_word_t := (others => '1');
  begin
-    --  The data bits
+    --  Compute which data bits have been altered.
+    --  If a data bit is altered, its corresponding ECC bits are altered too.
+    --  So, conversely (and because there is only one error), the altered ECC bits
+    --  designate the altered data bit.
    for i in 0 to 31 loop
      for k in 0 to 6 loop
        if syndrome_masks(k)(i) = '1' then
@@ -112,14 +122,7 @@ package body secded_32b_pkg is
      end loop;
    end loop;

-    if f_or (result) = '1' then
-      corrected_word := data (38 downto 32) & (result xor data(31 downto 0));
-    elsif f_or (syndrome) = '1' then
-      corrected_word := (syndrome & result) xor data;
-    else
-      corrected_word := "0000000" & x"00000000";
-    end if;
-
-    return corrected_word;
+    --  Return the fixed ecc+data.
+    return (syndrome xor ecc) & (result xor data);
  end f_fix_error;
-end secded_32b_pkg;
\ No newline at end of file
+end secded_32b_pkg;
--- a/modules/radtol/secded_ecc.vhd
+++ b/modules/radtol/secded_ecc.vhd
@@ -251,7 +251,7 @@ begin
            ack_correction  <= '0';
            done_w          <= '0';
            if req_correction = '1' and ack_correction = '0' then
-              q_ram        <= f_fix_error (syndrome, d_ram_i);
+              q_ram        <= f_fix_error (syndrome, d_ram_i(38 downto 32), d_ram_i (31 downto 0));
              we_ram_o     <= '1';
              fsm_write    <= check_write;
            elsif we = '1' then

--- a/testbench/radtol/tb_secded_32b_pkg.vhd
+++ b/testbench/radtol/tb_secded_32b_pkg.vhd
+library ieee;
+use ieee.std_logic_1164.all;
+use work.secded_32b_pkg.all;
+
+entity tb_secded_32b_pkg is
+end tb_secded_32b_pkg;
+
+architecture behav of tb_secded_32b_pkg is
+  function image(v : std_logic_vector) return string
+  is
+    alias va : std_logic_vector(1 to v'length) is v;
+    variable res : string (va'range);
+  begin
+    for i in va'range loop
+      if va (i) = '1' then
+        res (i) := '1';
+      else
+        res (i) := '0';
+      end if;
+    end loop;
+    return res;
+  end image;
+
+  signal data, err, data2 : std_logic_vector (31 downto 0);
+  signal ecc, ecc2, syndrome : std_logic_vector(6 downto 0);
+  signal cor : std_logic_vector(38 downto 0);
+begin
+  process
+  begin
+    data <= x"789a_d3f5";
+    wait for 1 ns;
+    ecc <= f_calc_ecc (data);
+
+    for i in 0 to 38 loop
+      err <= (others => '0');
+      if i < 32 then
+        err (i) <= '1';
+        wait for 1 ns;
+        data2 <= data xor err;
+        wait for 1 ns;
+        ecc2 <= f_calc_ecc (data2);
+      else
+        err (i - 32) <= '1';
+        wait for 1 ns;
+        ecc2 <= ecc xor err(6 downto 0);
+        data2 <= data;
+      end if;
+      wait for 1 ns;
+      syndrome <= ecc2 xor ecc;
+      wait for 1 ns;
+      cor <= f_fix_error(syndrome, ecc2, data2);
+      wait for 1 ns;
+      report "data:  " & image (data) & ", ecc:  " & image (ecc) & ", err: " & image (err) & ", ecc/err: " & image(ecc2);
+      report "cdata: " & image (cor(31 downto 0)) & ", cecc: " & image(cor(38 downto 32)) & " syndrome: " & image(syndrome);
+      assert cor(31 downto 0) = data severity failure;
+      assert cor(38 downto 32) = ecc severity failure;
+    end loop;
+    report "end of test";
+    wait;
+  end process;
+end behav;