Merge branch 'axi-test-suite' into 'proposed_master'

Adding Testbench for AXI cores See merge request !28

Merge branch 'axi-test-suite' into 'proposed_master'
Adding Testbench for AXI cores See merge request !28
a0e0f2e5 · Tristan Gingold · 50d0e9fe · 631c62f8 · a0e0f2e5 · a0e0f2e5
Commit a0e0f2e5 authored Jan 16, 2023 by Tristan Gingold
30 changed files
--- a/.gitmodules
+++ b/.gitmodules
+[submodule "testbench/osvvm/upstream"]
+	path = testbench/osvvm/upstream
+	url = https://github.com/OSVVM/OSVVM.git
--- a/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd
+++ b/modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd
 -------------------------------------------------------------------------------
-- Title      : AXI4Full64 to AXI4Lite32 bridge
+-- Title      : AXI4Lite to AXI4Full bridge
 -- Project    : General Cores
 -------------------------------------------------------------------------------
-- File       : axi4lite32_axi4full64_bridge.vhd
+-- File       : axi4lite_axi4full_bridge.vhd
 -- Company    : CERN
 -- Platform   : FPGA-generics
 -- Standard   : VHDL '93
@@ -230,8 +230,11 @@ begin

  --  Read part.
  m_araddr <= raddr;
-  s_rdata <= rdata;
-  s_rid <= rid;
+  s_rdata  <= rdata;
+  s_rid    <= rid;
+
+  s_rlast <= '1' when (unsigned(rlen)=0 and s_rready = '1' and s_rvalid = '1')
+             else '0';

  process (clk_i)
  begin
@@ -240,7 +243,6 @@ begin
        rstate <= RD_IDLE;
        s_arready <= '1';
        s_rvalid <= '0';
-        s_rlast <= '0';
        m_arvalid <= '0';
        m_rready <= '0';
        raddr <= (others => 'X');
@@ -275,6 +277,7 @@ begin
              m_arvalid <= '0';
            end if;
            if m_rvalid = '1' then
+              m_rready <= '0';
              --  Read data.  Address must have been acked.
              --  According to A3.4.3 of AXI4 spec, the AXI4 bus is little
              --  endian.
@@ -283,11 +286,6 @@ begin
              --  To master.
              rstate <= RD_SLAVE;
              s_rresp <= RSP_OKAY;
-              if rlen = (g_LEN_WIDTH - 1 downto 0 => '0') then
-                s_rlast <= '1';
-              else
-                s_rlast <= '0';
-              end if;
              s_rvalid <= '1';
            end if;


--- a/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd
+++ b/modules/axi/z7_axi_gpio_expander/axi_gpio_expander.vhd
@@ -134,17 +134,17 @@ architecture behav of axi_gpio_expander is
    return tmp;
  end function;
  -------------------------------------------
-  function f_update_gpio_in (orig : std_logic_vector; rdata : std_logic_vector; bank : integer)
+  function f_update_gpio_in (orig : std_logic_vector; rd_data : std_logic_vector; bank : integer)
    return std_logic_vector is
    variable tmp : std_logic_vector(g_num-1 downto 0);
  begin
    tmp := orig;
    if (bank = 0 and g_num >= c_GPIOPS_BANK0) then
-      tmp(c_GPIOPS_BANK0-1 downto 0) := rdata;
+      tmp(c_GPIOPS_BANK0-1 downto 0) := rd_data;
    elsif (bank = 0 and g_num < c_GPIOPS_BANK0) then
-      tmp := rdata(g_num-1 downto 0);
+      tmp := rd_data(g_num-1 downto 0);
    else
-      tmp(g_num-1 downto c_GPIOPS_BANK0) := rdata(g_num-c_GPIOPS_BANK0-1 downto 0);
+      tmp(g_num-1 downto c_GPIOPS_BANK0) := rd_data(g_num-c_GPIOPS_BANK0-1 downto 0);
    end if;
    return tmp;
  end function;
@@ -295,7 +295,7 @@ begin
              -- write accepted, let's proceed
              BREADY <= '0';
              state <= INIT_WRITE_OUT;
-            elsif (BVALID = '1' and BRESP = c_AXI4_RESP_OKAY) then 
+            elsif (BVALID = '1' and BRESP = c_AXI4_RESP_OKAY) then
              -- nothing to update in GPIO_OUT, skip to GPIO reading
              BREADY <= '0';
              state <= INIT_READ;
@@ -409,7 +409,7 @@ begin
            else -- current_bank = 0 and g_num =< c_GPIOPS_BANK0
              -- Only Bank0 is used, reset refresh_all flag, Bank0 registers are
              -- all set here.
-              refresh_all <= '0'; 
+              refresh_all <= '0';
            end if;
            state <= IDLE;


--- a/testbench/Makefile
+++ b/testbench/Makefile
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+
+# This Makefile can be called by the Continuous Integration (CI) tool to execute all
+# testbenches added for CI
+
+# AXI4 cores
+TB_DIRS+=axi/axi4lite_wb_bridge
+TB_DIRS+=axi/z7_axi_gpio_expander
+TB_DIRS+=axi/axi4lite32_axi4full64_bridge
+TB_DIRS+=axi/axi4lite_axi4full_bridge
+
+.PHONY: $(TB_DIRS)
+
+all: $(TB_DIRS) summary
+
+$(TB_DIRS):
+	@echo "Run HDLMAKE"
+	@cd "$@"; \
+	hdlmake 2>&1
+	@echo "Run make"
+	@$(MAKE) -C $@ $(TARGET)
+
+	@echo "Run ghdl"
+	@cd "$@" ;\
+	./run.sh
+	@echo "ghdl returned $$?"
+
+summary: $(TB_DIRS)
+	@echo "-------------------------------------------------------------------"
+	@echo "Summary:"
+	@for d in $(TB_DIRS); do \
+		if [ -f $$d/transcript ]; then \
+			echo "Warnings for $$d:"; \
+			cat $$d/transcript | grep Warning; \
+			if [ $$? -eq 1 ]; then echo "None"; fi ;\
+			echo "Errors for $$d:"; \
+			cat $$d/transcript | grep Error; \
+			if [ $$? -eq 1 ]; then echo "None"; fi ;\
+		else \
+			echo "No transcript file for $$d"; \
+		fi \
+	done
+
+clean:
+	@for d in $(TB_DIRS); do \
+		if [ -f $$d/Makefile ]; then \
+			$(MAKE) -C $$d $@; \
+			rm -f $$d/Makefile; \
+		fi \
+	done
--- a/testbench/README.md
+++ b/testbench/README.md
+# Description
+The majority of the general cores have their own testbench written in VHDL and as a verification methodology, OSVVM is used. There are also some testbenches which are written in SystemVerilog.
+
+The common features of each test are:
+  - Randomization of the input signals
+  - FSM coverage (when there are FSM in the RTL design), results are shown at the end of the simulation
+  - Assertions are used to verify aspects of the core's functionality, cumply with the specifications
+
+There are two options for the users, in order to run these tests. First is to run them all by using the Makefile in the current directory. This Makefile contains all the VHDL tests. Second option, is to run each test individually.
+
+## Requirements
+  - [hdlmake](https://hdlmake.readthedocs.io/en/master/#install-hdlmake-package)
+  - [ghdl](https://ghdl.github.io/ghdl/development/building/index.html#build)
+
+## Set up environment
+  - OSVVM is a dependency for most of these testbenches. It is already included as a git submodule. Therefore, it is necessary to run at least once `git submodule update --init` before running these testbenches.
+
+## How to test
+```console
+hdlmake makefile
+make
+./run.sh
+```
+ Waveform option:
+```console
+ ./run.sh --wave=waveform.ghw
+```
--- a/testbench/axi/axi4lite32_axi4full64_bridge/.gitignore
+++ b/testbench/axi/axi4lite32_axi4full64_bridge/.gitignore
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+*
+!.gitignore
+!Manifest.py
+!*.vhd
+!*.cheby
+!run.sh
--- a/testbench/axi/axi4lite32_axi4full64_bridge/Manifest.py
+++ b/testbench/axi/axi4lite32_axi4full64_bridge/Manifest.py
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+action="simulation"
+sim_tool="ghdl"
+target="generic"
+ghdl_opt="--std=08 -frelaxed-rules -Wno-hide"
+sim_top="tb_axi4lite32_axi4full64_bridge"
+
+files="tb_axi4lite32_axi4full64_bridge.vhd"
+
+modules={"local" : ["../../../",
+                    "../../osvvm/",
+                    "../../../modules/wishbone",
+                    "../../../modules/axi"]}
+
--- a/testbench/axi/axi4lite32_axi4full64_bridge/README.md
+++ b/testbench/axi/axi4lite32_axi4full64_bridge/README.md
+## Description
+Testbench for [axi4lite32_axi4full64_bridge](../../modules/axi/axi4lite32_axi4full64_bridge/axi4lite32_axi4full64_bridge.vhd) which is a bridge from AXI4Lite32 to AXI4Full64. Master is the axi4lite and the slave is axi4full.
+
+NOTE: By default, the simulation time is 4ms. For any change in this, run the test and pass the simulation time as an argument to this script:
+```console
+./run.sh <simulation time>
+```
--- a/testbench/axi/axi4lite32_axi4full64_bridge/run.sh
+++ b/testbench/axi/axi4lite32_axi4full64_bridge/run.sh
+#!/bin/bash -e
+
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+#This is a simple script to run simulations in GHDL
+
+TB=tb_axi4lite32_axi4full64_bridge
+
+if [ -z "$1" ]; then
+  TIME="4"
+else
+  TIME="$1"
+fi;
+
+echo "Running simulation for $TB"
+
+ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_sim_time=$TIME
--- a/testbench/axi/axi4lite32_axi4full64_bridge/tb_axi4lite32_axi4full64_bridge.vhd
+++ b/testbench/axi/axi4lite32_axi4full64_bridge/tb_axi4lite32_axi4full64_bridge.vhd
--- a/testbench/axi/axi4lite_axi4full_bridge/.gitignore
+++ b/testbench/axi/axi4lite_axi4full_bridge/.gitignore
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+*
+!.gitignore
+!Manifest.py
+!*.vhd
+!*.cheby
+!run.sh
--- a/testbench/axi/axi4lite_axi4full_bridge/Manifest.py
+++ b/testbench/axi/axi4lite_axi4full_bridge/Manifest.py
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+
+action  ="simulation"
+sim_tool="ghdl"
+target  ="generic"
+ghdl_opt="--std=08 -frelaxed-rules -Wno-hide"
+sim_top ="tb_axi4lite_axi4full_bridge"
+
+files ="tb_axi4lite_axi4full_bridge.vhd"
+
+modules = {"local" : ["../../../",
+                    "../../osvvm/",
+                      ]}
+
--- a/testbench/axi/axi4lite_axi4full_bridge/README.md
+++ b/testbench/axi/axi4lite_axi4full_bridge/README.md
+## Description
+Testbench for [axi4lite_axi4full_bridge](../../modules/axi/axi4lite_axi4full_bridge/axi4lite_axi4full_bridge.vhd) which is a bridge from AXI4Lite to AXI4Full. Master is the axi4lite and the slave is axi4full.
+
+NOTE: By default, the simulation time is 4ms. For any change in this, run the test and pass the simulation time as an argument (integer) to this script:
+```console
+./run.sh <simulation time>
+```
--- a/testbench/axi/axi4lite_axi4full_bridge/run.sh
+++ b/testbench/axi/axi4lite_axi4full_bridge/run.sh
+#!/bin/bash -e
+
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+#This is a simple script to run simulations in GHDL
+
+TB=tb_axi4lite_axi4full_bridge
+
+if [ -z "$1" ]; then
+  TIME="4"
+else
+  TIME="$1"
+fi;
+
+echo "Running simulation for $TB"
+
+ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_sim_time=$TIME
+
--- a/testbench/axi/axi4lite_axi4full_bridge/tb_axi4lite_axi4full_bridge.vhd
+++ b/testbench/axi/axi4lite_axi4full_bridge/tb_axi4lite_axi4full_bridge.vhd
--- a/testbench/axi/axi4lite_wb_bridge/.gitignore
+++ b/testbench/axi/axi4lite_wb_bridge/.gitignore
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+*
+!.gitignore
+!Manifest.py
+!*.vhd
+!*.cheby
+!run.sh
--- a/testbench/axi/axi4lite_wb_bridge/Manifest.py
+++ b/testbench/axi/axi4lite_wb_bridge/Manifest.py
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+action="simulation"
+sim_tool="ghdl"
+target="generic"
+ghdl_opt="--std=08 -frelaxed-rules -Wno-hide"
+sim_top="tb_xaxi4lite_wb_bridge"
+
+files="tb_xaxi4lite_wb_bridge.vhd"
+
+modules={"local" : ["../../../",
+                    "../../osvvm/",
+                    "../../../modules/wishbone",
+                    "../../../modules/axi"]}
+
--- a/testbench/axi/axi4lite_wb_bridge/README.md
+++ b/testbench/axi/axi4lite_wb_bridge/README.md
+## Description
+Testbench for [axi4lite_wb_bridge](../../modules/axi/axi4lite_wb_bridge/xaxi4lite_wb_bridge.vhd) which is a bridge from AXI4 Lite to Wishbone. In this core, the Master is AXI4 Lite and Slave is Wishbone.
+
+NOTE: By default, the simulation time is 4ms. To change this, run the test and pass the simulation time as an argument (integer) to this script:
+```console
+./run.sh <simulation time>
+```
--- a/testbench/axi/axi4lite_wb_bridge/run.sh
+++ b/testbench/axi/axi4lite_wb_bridge/run.sh
+#!/bin/bash -e
+
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+#This is a simple script to run simulations in GHDL
+
+TB=tb_xaxi4lite_wb_bridge
+
+if [ -z "$1" ]; then
+  TIME="4"
+else
+  TIME="$1"
+fi;
+
+echo "Running simulation for $TB"
+
+ghdl -r --std=08 -frelaxed-rules $TB -gg_seed=$RANDOM -gg_sim_time=$TIME
+
+
--- a/testbench/axi/axi4lite_wb_bridge/tb_xaxi4lite_wb_bridge.vhd
+++ b/testbench/axi/axi4lite_wb_bridge/tb_xaxi4lite_wb_bridge.vhd
--- a/testbench/axi/z7_axi_gpio_expander/.gitignore
+++ b/testbench/axi/z7_axi_gpio_expander/.gitignore
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+*
+!.gitignore
+!Manifest.py
+!*.vhd
+!*.cheby
+!run.sh
--- a/testbench/axi/z7_axi_gpio_expander/Manifest.py
+++ b/testbench/axi/z7_axi_gpio_expander/Manifest.py
-target = "xilinx"
-action = "simulation"
-sim_tool = "modelsim"
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+target     = "xilinx"
+action     = "simulation"
+sim_tool   = "ghdl"
 top_module = "sim_top_ps_gpio"
 syn_device = "XC7Z010"
+ghdl_opt = "--std=08 -frelaxed-rules -Wno-hide"

 files = [ "gpio_axi.vhd", "sim_top_ps_gpio.vhd" ]

-modules = { "local" : ["../../../"] }
+modules = { "local" : ["../../../",
+                       "../../osvvm/"] }

--- a/testbench/axi/z7_axi_gpio_expander/gpio.cheby
+++ b/testbench/axi/z7_axi_gpio_expander/gpio.cheby
+-- SPDX-FileCopyrightText: 2023 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 memory-map:
  bus: axi4-lite-32
  name: axi_gpio

--- a/testbench/axi/z7_axi_gpio_expander/gpio_axi.vhd
+++ b/testbench/axi/z7_axi_gpio_expander/gpio_axi.vhd
+-- SPDX-FileCopyrightText: 2023 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -78,7 +82,7 @@ begin
  wready <= axi_wip and wr_ack_int;
  bvalid <= axi_wdone;
  process (aclk, areset_n) begin
-    if areset_n = '0' then 
+    if areset_n = '0' then
      axi_wip <= '0';
      axi_wdone <= '0';
    elsif rising_edge(aclk) then
@@ -93,7 +97,7 @@ begin
  arready <= axi_rip and rd_ack_int;
  rvalid <= axi_rdone;
  process (aclk, areset_n) begin
-    if areset_n = '0' then 
+    if areset_n = '0' then
      axi_rip <= '0';
      axi_rdone <= '0';
      rdata <= (others => '0');
@@ -117,7 +121,7 @@ begin

  -- Process for write requests.
  process (aclk, areset_n) begin
-    if areset_n = '0' then 
+    if areset_n = '0' then
      wr_ack_int <= '0';
      out_b0_reg <= "00000000000000000000000000000000";
      out_b1_reg <= "00000000000000000000000000000000";
@@ -128,41 +132,41 @@ begin
    elsif rising_edge(aclk) then
      wr_ack_int <= '0';
      case awaddr(15 downto 2) is
-      when "10100000010000" => 
+      when "10100000010000" =>
        -- Register out_b0
        if wr_int = '1' then
          out_b0_reg <= wdata;
        end if;
        wr_ack_int <= wr_int;
-      when "10100000010001" => 
+      when "10100000010001" =>
        -- Register out_b1
        if wr_int = '1' then
          out_b1_reg <= wdata;
        end if;
        wr_ack_int <= wr_int;
-      when "10100000011000" => 
+      when "10100000011000" =>
        -- Register in_b0
-      when "10100000011001" => 
+      when "10100000011001" =>
        -- Register in_b1
-      when "10100010000001" => 
+      when "10100010000001" =>
        -- Register dir_b0
        if wr_int = '1' then
          dir_b0_reg <= wdata;
        end if;
        wr_ack_int <= wr_int;
-      when "10100010000010" => 
+      when "10100010000010" =>
        -- Register oen_b0
        if wr_int = '1' then
          oen_b0_reg <= wdata;
        end if;
        wr_ack_int <= wr_int;
-      when "10100010010001" => 
+      when "10100010010001" =>
        -- Register dir_b1
        if wr_int = '1' then
          dir_b1_reg <= wdata;
        end if;
        wr_ack_int <= wr_int;
-      when "10100010010010" => 
+      when "10100010010010" =>
        -- Register oen_b1
        if wr_int = '1' then
          oen_b1_reg <= wdata;
@@ -176,36 +180,36 @@ begin

  -- Process for registers read.
  process (aclk, areset_n) begin
-    if areset_n = '0' then 
+    if areset_n = '0' then
      rd_ack1_int <= '0';
      reg_rdat_int <= (others => 'X');
    elsif rising_edge(aclk) then
      reg_rdat_int <= (others => '0');
      case araddr(15 downto 2) is
-      when "10100000010000" => 
+      when "10100000010000" =>
        -- out_b0
        rd_ack1_int <= rd_int;
-      when "10100000010001" => 
+      when "10100000010001" =>
        -- out_b1
        rd_ack1_int <= rd_int;
-      when "10100000011000" => 
+      when "10100000011000" =>
        -- in_b0
        reg_rdat_int <= in_b0_i;
        rd_ack1_int <= rd_int;
-      when "10100000011001" => 
+      when "10100000011001" =>
        -- in_b1
        reg_rdat_int <= in_b1_i;
        rd_ack1_int <= rd_int;
-      when "10100010000001" => 
+      when "10100010000001" =>
        -- dir_b0
        rd_ack1_int <= rd_int;
-      when "10100010000010" => 
+      when "10100010000010" =>
        -- oen_b0
        rd_ack1_int <= rd_int;
-      when "10100010010001" => 
+      when "10100010010001" =>
        -- dir_b1
        rd_ack1_int <= rd_int;
-      when "10100010010010" => 
+      when "10100010010010" =>
        -- oen_b1
        rd_ack1_int <= rd_int;
      when others =>
@@ -219,35 +223,35 @@ begin
    -- By default ack read requests
    dato <= (others => '0');
    case araddr(15 downto 2) is
-    when "10100000010000" => 
+    when "10100000010000" =>
      -- out_b0
      dato <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
-    when "10100000010001" => 
+    when "10100000010001" =>
      -- out_b1
      dato <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
-    when "10100000011000" => 
+    when "10100000011000" =>
      -- in_b0
      dato <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
-    when "10100000011001" => 
+    when "10100000011001" =>
      -- in_b1
      dato <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
-    when "10100010000001" => 
+    when "10100010000001" =>
      -- dir_b0
      dato <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
-    when "10100010000010" => 
+    when "10100010000010" =>
      -- oen_b0
      dato <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
-    when "10100010010001" => 
+    when "10100010010001" =>
      -- dir_b1
      dato <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;
-    when "10100010010010" => 
+    when "10100010010010" =>
      -- oen_b1
      dato <= reg_rdat_int;
      rd_ack_int <= rd_ack1_int;

--- a/testbench/axi/z7_axi_gpio_expander/run.do
+++ b/testbench/axi/z7_axi_gpio_expander/run.do
-vsim -t 10fs work.sim_top_ps_gpio -voptargs="+acc"
-set StdArithNoWarnings 1
-set NumericStdNoWarnings 1
-do wave.do
-radix -hexadecimal
-run 200ms
-wave zoomfull
-radix -hexadecimal
--- a/testbench/axi/z7_axi_gpio_expander/run.sh
+++ b/testbench/axi/z7_axi_gpio_expander/run.sh
+#!/bin/bash -e
+
+# SPDX-FileCopyrightText: 2023 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0+
+
+#This is a simple script to run simulations in GHDL
+
+TB=sim_top_ps_gpio
+
+echo "Running simulation for $TB"
+
+ghdl -r --std=08 -frelaxed-rules $TB --stop-time=2ms
+echo "********************************************"
--- a/testbench/axi/z7_axi_gpio_expander/sim_top_ps_gpio.vhd
+++ b/testbench/axi/z7_axi_gpio_expander/sim_top_ps_gpio.vhd
 -------------------------------------------------------------------------------
+-- SPDX-FileCopyrightText: 2023 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+-------------------------------------------------------------------------------
 -- Title      : AXI PS_GPIO Expander for Zynq-7 Testbench
 -- Project    : General Cores
 -------------------------------------------------------------------------------
@@ -16,33 +20,35 @@
 -- using xsim or GHDL.
 --
 -------------------------------------------------------------------------------
-- Copyright (c) 2019 CERN
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
+
+--=============================================================================
+--                            Libraries & Packages                           --
+--=============================================================================

 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 use ieee.std_logic_misc.all;

+--=============================================================================
+--                    Entity declaration for sim_top_ps_gpio                 --
+--=============================================================================
+
 entity sim_top_ps_gpio is
 end sim_top_ps_gpio;

+--==============================================================================
+--                           Architecture declaration                         --
+--==============================================================================
+
 architecture behav of sim_top_ps_gpio is
+
+  -- Constants
  constant c_PERIOD : time := 10 ns;
  constant c_NUM    : integer := 54;

+  -- Signals
  signal clk, rst_n : std_logic;
-
  signal ARVALID : std_logic;
  signal AWVALID : std_logic;
  signal BREADY  : std_logic;
@@ -105,7 +111,7 @@ begin
    ARADDR  =>  ARADDR,
    AWADDR  =>  AWADDR,
    WDATA   =>  WDATA,
-    WSTRB   =>  WSTRB, 
+    WSTRB   =>  WSTRB,
    ARREADY =>  ARREADY,
    AWREADY =>  AWREADY,
    BVALID  =>  BVALID,
@@ -128,7 +134,7 @@ begin
    araddr    => ARADDR(15 downto 2),
    awaddr    => AWADDR(15 downto 2),
    wdata     => WDATA,
-    wstrb     => WSTRB, 
+    wstrb     => WSTRB,
    arready   => ARREADY,
    awready   => AWREADY,
    bvalid    => BVALID,
@@ -194,4 +200,34 @@ begin
    wait;
  end process;

+  --==============================================================================
+  --                              Assertions                                    --
+  --==============================================================================
+
+  -- Check AXI-4 LITE signals
+  p_axi_check : process(AWREADY,WREADY,BVALID,ARREADY,RVALID)
+  begin
+    if falling_edge(AWREADY) then
+      assert (AWVALID = '0')
+      report "Wrong AWVALID for AWREADY LOW" severity failure;
+    end if;
+    if falling_edge(WREADY) then
+      assert (WVALID = '0')
+      report "Wrong WVALID for WREADY LOW" severity failure;
+    end if;
+    if falling_edge(BVALID) then
+      assert (BREADY = '0')
+      report "Wrong BREADY for BVALID LOW" severity failure;
+    end if;
+    if falling_edge(ARREADY) then
+      assert (ARVALID = '0')
+      report "Wrong ARVALID for ARREADY LOW" severity failure;
+    end if;
+    if falling_edge(RVALID) then
+      assert (RREADY = '0')
+      report "Wrong RREADY for RVALID LOW" severity failure;
+    end if;
+  end process;
+
+
 end behav;
--- a/testbench/axi/z7_axi_gpio_expander/wave.do
+++ b/testbench/axi/z7_axi_gpio_expander/wave.do
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /sim_top_ps_gpio/clk
-add wave -noupdate /sim_top_ps_gpio/rst_n
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/ARVALID
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/AWVALID
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/BREADY
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/RREADY
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/WVALID
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/ARADDR
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/AWADDR
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/WDATA
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/WSTRB
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/ARREADY
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/AWREADY
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/BVALID
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/RVALID
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/WREADY
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/BRESP
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/RRESP
-add wave -noupdate -expand -group AXI /sim_top_ps_gpio/RDATA
-add wave -noupdate /sim_top_ps_gpio/error_b1
-add wave -noupdate /sim_top_ps_gpio/out_b0
-add wave -noupdate /sim_top_ps_gpio/out_b1
-add wave -noupdate /sim_top_ps_gpio/dir_b0
-add wave -noupdate /sim_top_ps_gpio/dir_b1
-add wave -noupdate /sim_top_ps_gpio/oen_b0
-add wave -noupdate /sim_top_ps_gpio/oen_b1
-add wave -noupdate /sim_top_ps_gpio/gpio_out
-add wave -noupdate /sim_top_ps_gpio/gpio_oe
-add wave -noupdate /sim_top_ps_gpio/gpio_dir
-add wave -noupdate /sim_top_ps_gpio/gpio_in
-add wave -noupdate /sim_top_ps_gpio/U_EXP/state
-add wave -noupdate /sim_top_ps_gpio/U_EXP/gpio_oe_prev
-add wave -noupdate /sim_top_ps_gpio/U_EXP/gpio_dir_prev
-add wave -noupdate /sim_top_ps_gpio/U_EXP/gpio_out_prev
-add wave -noupdate /sim_top_ps_gpio/U_EXP/gpio_oe_changed
-add wave -noupdate /sim_top_ps_gpio/U_EXP/gpio_dir_changed
-add wave -noupdate /sim_top_ps_gpio/U_EXP/gpio_out_changed
-add wave -noupdate /sim_top_ps_gpio/U_EXP/refresh_all
-add wave -noupdate /sim_top_ps_gpio/U_EXP/current_bank
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {0 fs} 0}
-quietly wave cursor active 0
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 1
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits fs
-update
-WaveRestoreZoom {0 fs} {5780 fs}
--- a/testbench/osvvm/Manifest.py
+++ b/testbench/osvvm/Manifest.py
+library="osvvm"
+
+files = [
+    "upstream/AlertLogPkg.vhd",
+    "upstream/CoveragePkg.vhd",
+    "upstream/MemoryGenericPkg.vhd",
+    "upstream/MemoryPkg.vhd",
+    "upstream/MemorySupportPkg.vhd",
+    "upstream/MessageListPkg.vhd",
+    "upstream/MessagePkg.vhd",
+    "upstream/NamePkg.vhd",
+    "upstream/NameStorePkg.vhd",
+    "upstream/OsvvmContext.vhd",
+    "upstream/OsvvmGlobalPkg.vhd",
+    "upstream/OsvvmTypesPkg.vhd",
+    "upstream/RandomBasePkg.vhd",
+    "upstream/RandomPkg.vhd",
+    "upstream/RandomProcedurePkg.vhd",
+    "upstream/ReportPkg.vhd",
+    "upstream/ResizePkg.vhd",
+    "upstream/ResolutionPkg.vhd",
+    "upstream/ScoreboardGenericPkg.vhd",
+    "upstream/ScoreboardPkg_int.vhd",
+    "upstream/ScoreboardPkg_slv.vhd",
+    "upstream/SortListPkg_int.vhd",
+    "upstream/TbUtilPkg.vhd",
+    "upstream/TextUtilPkg.vhd",
+    "upstream/TranscriptPkg.vhd",
+    "upstream/VendorCovApiPkg.vhd",
+]
+
--- a/upstream @ 0bced010
+++ b/upstream @ 0bced010
+Subproject commit 0bced0107438a612b8656d5ae80a6d1a32f22b81