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Platform-independent core collection
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Platform-independent core collection
Commits
5bc55a5a
Commit
5bc55a5a
authored
Jan 16, 2023
by
Dimitris Lampridis
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Introduce OSVVM dependency as submodule
parent
ddb03954
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7 changed files
with
48 additions
and
8 deletions
+48
-8
.gitmodules
.gitmodules
+3
-0
Manifest.py
testbench/axi/axi4lite32_axi4full64_bridge/Manifest.py
+2
-1
Manifest.py
testbench/axi/axi4lite_axi4full_bridge/Manifest.py
+4
-2
Manifest.py
testbench/axi/axi4lite_wb_bridge/Manifest.py
+3
-1
Manifest.py
testbench/axi/z7_axi_gpio_expander/Manifest.py
+4
-4
Manifest.py
testbench/osvvm/Manifest.py
+31
-0
upstream
testbench/osvvm/upstream
+1
-0
No files found.
.gitmodules
0 → 100644
View file @
5bc55a5a
[submodule "testbench/osvvm/upstream"]
path = testbench/osvvm/upstream
url = https://github.com/OSVVM/OSVVM.git
testbench/axi/axi4lite32_axi4full64_bridge/Manifest.py
View file @
5bc55a5a
action
=
"simulation"
sim_tool
=
"ghdl"
target
=
"generic"
ghdl_opt
=
"--std=08 -frelaxed-rules"
ghdl_opt
=
"--std=08 -frelaxed-rules
-Wno-hide
"
sim_top
=
"tb_axi4lite32_axi4full64_bridge"
files
=
"tb_axi4lite32_axi4full64_bridge.vhd"
modules
=
{
"local"
:
[
"../../../"
,
"../../osvvm/"
,
"../../../modules/wishbone"
,
"../../../modules/axi"
]}
testbench/axi/axi4lite_axi4full_bridge/Manifest.py
View file @
5bc55a5a
action
=
"simulation"
sim_tool
=
"ghdl"
target
=
"generic"
ghdl_opt
=
"--std=08 -frelaxed-rules"
ghdl_opt
=
"--std=08 -frelaxed-rules
-Wno-hide
"
sim_top
=
"tb_axi4lite_axi4full_bridge"
files
=
"tb_axi4lite_axi4full_bridge.vhd"
modules
=
{
"local"
:
[
"../../../"
,]}
modules
=
{
"local"
:
[
"../../../"
,
"../../osvvm/"
,
]}
testbench/axi/axi4lite_wb_bridge/Manifest.py
View file @
5bc55a5a
action
=
"simulation"
sim_tool
=
"ghdl"
target
=
"generic"
ghdl_opt
=
"--std=08 -frelaxed-rules"
ghdl_opt
=
"--std=08 -frelaxed-rules
-Wno-hide
"
sim_top
=
"tb_xaxi4lite_wb_bridge"
files
=
"tb_xaxi4lite_wb_bridge.vhd"
modules
=
{
"local"
:
[
"../../../"
,
"../../osvvm/"
,
"../../../modules/wishbone"
,
"../../../modules/axi"
]}
testbench/axi/z7_axi_gpio_expander/Manifest.py
View file @
5bc55a5a
target
=
"xilinx"
action
=
"simulation"
sim_tool
=
"ghdl"
#"modelsim"
sim_tool
=
"ghdl"
top_module
=
"sim_top_ps_gpio"
syn_device
=
"XC7Z010"
# This can be deleted when GHDL not used
ghdl_opt
=
"--std=08 -frelaxed-rules"
ghdl_opt
=
"--std=08 -frelaxed-rules -Wno-hide"
files
=
[
"gpio_axi.vhd"
,
"sim_top_ps_gpio.vhd"
]
modules
=
{
"local"
:
[
"../../../"
]
}
modules
=
{
"local"
:
[
"../../../"
,
"../../osvvm/"
]
}
testbench/osvvm/Manifest.py
0 → 100644
View file @
5bc55a5a
library
=
"osvvm"
files
=
[
"upstream/AlertLogPkg.vhd"
,
"upstream/CoveragePkg.vhd"
,
"upstream/MemoryGenericPkg.vhd"
,
"upstream/MemoryPkg.vhd"
,
"upstream/MemorySupportPkg.vhd"
,
"upstream/MessageListPkg.vhd"
,
"upstream/MessagePkg.vhd"
,
"upstream/NamePkg.vhd"
,
"upstream/NameStorePkg.vhd"
,
"upstream/OsvvmContext.vhd"
,
"upstream/OsvvmGlobalPkg.vhd"
,
"upstream/OsvvmTypesPkg.vhd"
,
"upstream/RandomBasePkg.vhd"
,
"upstream/RandomPkg.vhd"
,
"upstream/RandomProcedurePkg.vhd"
,
"upstream/ReportPkg.vhd"
,
"upstream/ResizePkg.vhd"
,
"upstream/ResolutionPkg.vhd"
,
"upstream/ScoreboardGenericPkg.vhd"
,
"upstream/ScoreboardPkg_int.vhd"
,
"upstream/ScoreboardPkg_slv.vhd"
,
"upstream/SortListPkg_int.vhd"
,
"upstream/TbUtilPkg.vhd"
,
"upstream/TextUtilPkg.vhd"
,
"upstream/TranscriptPkg.vhd"
,
"upstream/VendorCovApiPkg.vhd"
,
]
upstream
@
0bced010
Subproject commit 0bced0107438a612b8656d5ae80a6d1a32f22b81
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