inferred_async_fifo: avoid nested 'others' clause in signal initialization to…

inferred_async_fifo: avoid nested 'others' clause in signal initialization to keep ISE (Virtex5) happy

inferred_async_fifo: avoid nested 'others' clause in signal initialization to…
inferred_async_fifo: avoid nested 'others' clause in signal initialization to keep ISE (Virtex5) happy
66df5fa6 · Tomasz Wlostowski · 074d4468 · 66df5fa6
Commit 66df5fa6 authored Dec 16, 2021 by Tomasz Wlostowski
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inferred_async_fifo.vhd modules/genrams/common/inferred_async_fifo.vhd +11 -2

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--- a/modules/genrams/common/inferred_async_fifo.vhd
+++ b/modules/genrams/common/inferred_async_fifo.vhd
@@ -116,11 +116,20 @@ architecture syn of inferred_async_fifo is
    bin_x, gray_x   : t_counter;
  end record;

+  constant c_counters_reset_value : t_counter_block :=
+    ( bin => (others => '0'),
+      bin_next => (others => '0'),
+      gray  => (others => '0'),
+      gray_next  => (others => '0'),
+      bin_x => (others => '0'),
+      gray_x  => (others => '0') );
+  
+
  type t_mem_type is array (0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
  signal mem : t_mem_type := (others => (others => '0'));

-  signal rcb, wcb : t_counter_block := (others =>(others => '0'));
-
+  signal rcb, wcb : t_counter_block := c_counters_reset_value;
+  
  signal full_int, empty_int               : std_logic;
  signal almost_full_int, almost_empty_int : std_logic;
  signal going_full                        : std_logic;