This is necessary in order to properly "emulate" the previous implementation
of the gc_sync_ffs module.

Furthermore, a "new" module has been introduced, the gc_edge_detect, which
combines positive and negative pulse edge detection. gc_negedge and gc_posedge
have been rewritten to use internally the new gc_edge_detect.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is to avoid any confusion caused by g_SYNC_EDGE and g_EDGE
generics used in gc_sync, gc_sync_ffs and gc_sync_edge modules.

Also use capitals for generics as defined by our coding style.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This generic is dummy (does nothing), yet it is needed since the
generic component declaration in genram_pkg.vhd has such generic.
It has it, because the xilinx generic_dpram.vhd has such generic
and uses it.
TBD whether we want to attempt at providing similar functionality
for altera

Reported by Olof Kindgren (@olofk). See also merge request !4.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

1.0.4 - 2020-03-26
==================
https://www.ohwr.org/project/general-cores/tags/v1.0.4

Added
-----
- [hdl] VHDL functions to convert characters and strings to upper/lower case.
- [sw][i2c] Support for kernel greater than 4.7.
- [hdl] Separate synchroniser and edge detection modules.
- [hdl] 8b10b encoder.

Changed
-------
- [hdl] Rewritten the WB master interface used in simulations.
- [hdl] Reimplement gc_sync_ffs using new synchroniser and edge detectors.

Fixed
-----
- [sw][spi] Align polarity and phase for Rx and Tx.
- [hdl][i2c] Fix reset lock for I2C master.
- [hdl] Avoid cyclic dependencies for log2 ceiling functions.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Using the guidelines from here:
https://gitlab.cern.ch/be-co-ht-documents/project-management-guidelines/-/blob/master/how-to-write-changelog.rstSigned-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Instead of check for version here and there, the main code always uses
the latest API, and in a preprocessor ``if`` statement I implemented
the compatibility layer.

Like this it will be easier to apply patches from the kernel to our
local driver
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

sw:  Update spi-ocores

See merge request !3

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Also perform cleanup of sync and edge modules.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Reported by Olof Olof Kindgren (@olofk). See also merge request !4.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This allows them to be used right after in component declarations.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This is especially beneficial when trying to meet timing in the GN4124 core (on Spartan6), where the
async FIFOs are clocked on one side at 200MHz. Apparently, the KEEP_HIERARCHY attribute makes it
much easier for ISE 14.7 to reach timing closure.

It also helps in general to ensure that the synchronisation structures remain intact and do not get
merged in unpredictable ways with other parts of the design.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Align polarity and phase for SPI_OCORES_CTRL_Tx_NEG and SPI_OCORES_CTRL_Rx_NEG
with check for SPI_CPHA and mode(CPOL).
Signed-off-by: Mamta Shukla <mamta.ramendra.shukla@cern.ch>