Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
P
Platform-independent core collection
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
19
Issues
19
List
Board
Labels
Milestones
Merge Requests
5
Merge Requests
5
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Platform-independent core collection
Commits
f359d36e
Commit
f359d36e
authored
Mar 03, 2020
by
Tristan Gingold
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Add gc_negedge and gc_posedge.
parent
68ccc8ed
Hide whitespace changes
Inline
Side-by-side
Showing
4 changed files
with
109 additions
and
0 deletions
+109
-0
README.md
README.md
+3
-0
Manifest.py
modules/common/Manifest.py
+2
-0
gc_negedge.vhd
modules/common/gc_negedge.vhd
+52
-0
gc_posedge.vhd
modules/common/gc_posedge.vhd
+52
-0
No files found.
README.md
View file @
f359d36e
...
...
@@ -13,6 +13,9 @@ In [modules/common](modules/common) there are general purpose cores:
*
The package
[
matrix_pkg
](
modules/common/matrix_pkg.vhd
)
declares a 2d
array of std_logic, and some subprograms to handle it.
*
Edge detectors are provided by
[
gc_posedge
](
modules/common/gc_posedge.vhd
)
and
[
gc_negedge
](
modules/common/gc_negedge.vhd
)
.
*
For clock-domain crossing or asynchronous signal register, use
[
gc_sync
](
modules/common/gc_sync.vhd
)
. This is the basic synchronizer.
If you also need an edge detector, use
...
...
modules/common/Manifest.py
View file @
f359d36e
...
...
@@ -13,6 +13,8 @@ files = [
"gc_arbitrated_mux.vhd"
,
"gc_sync_register.vhd"
,
"gc_sync.vhd"
,
"gc_posedge.vhd"
,
"gc_negedge.vhd"
,
"gc_pulse_synchronizer.vhd"
,
"gc_pulse_synchronizer2.vhd"
,
"gc_frequency_meter.vhd"
,
...
...
modules/common/gc_negedge.vhd
0 → 100644
View file @
f359d36e
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- General Cores Library
-- https://www.ohwr.org/projects/general-cores
--------------------------------------------------------------------------------
--
-- unit name: gc_negedge
--
-- description: Simple falling edge detector. Combinatorial.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
gc_negedge
is
port
(
clk_i
:
in
std_logic
;
-- clock
rst_n_i
:
in
std_logic
;
-- reset
data_i
:
in
std_logic
;
-- input
pulse_o
:
out
std_logic
-- positive edge dectect output
);
end
entity
gc_negedge
;
architecture
arch
of
gc_negedge
is
signal
dff
:
std_logic
;
begin
pulse_o
<=
not
data_i
and
dff
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
dff
<=
'0'
;
else
dff
<=
data_i
;
end
if
;
end
if
;
end
process
;
end
arch
;
modules/common/gc_posedge.vhd
0 → 100644
View file @
f359d36e
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- General Cores Library
-- https://www.ohwr.org/projects/general-cores
--------------------------------------------------------------------------------
--
-- unit name: gc_posedge
--
-- description: Simple rising edge detector. Combinatorial.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
gc_posedge
is
port
(
clk_i
:
in
std_logic
;
-- clock
rst_n_i
:
in
std_logic
;
-- reset
data_i
:
in
std_logic
;
-- input
pulse_o
:
out
std_logic
-- positive edge dectect output
);
end
entity
gc_posedge
;
architecture
arch
of
gc_posedge
is
signal
dff
:
std_logic
;
begin
pulse_o
<=
data_i
and
not
dff
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
dff
<=
'0'
;
else
dff
<=
data_i
;
end
if
;
end
if
;
end
process
;
end
arch
;
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment