[hdl] added 8b10b encoder IP

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

[hdl] added 8b10b encoder IP
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
36e5eb0b · Tomasz Wlostowski · Dimitris Lampridis · a2ad05c2 · 36e5eb0b · 36e5eb0b
Commit 36e5eb0b authored Jun 14, 2019 by Tomasz Wlostowski Committed by Dimitris Lampridis Mar 06, 2020
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Manifest.py modules/common/Manifest.py +1 -0

gc_enc_8b10b.vhd modules/common/gc_enc_8b10b.vhd +333 -0

gencores_pkg.vhd modules/common/gencores_pkg.vhd +16 -0

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--- a/modules/common/Manifest.py
+++ b/modules/common/Manifest.py
@@ -33,6 +33,7 @@ files = [
    "gc_single_reset_gen.vhd",
    "gc_async_signals_input_stage.vhd",
    "gc_dec_8b10b.vhd",
+    "gc_enc_8b10b.vhd",
    "gc_dyn_extend_pulse.vhd",
    "gc_ds182x_interface.vhd",
    "gc_ds182x_readout/gc_ds182x_readout.vhd",

--- a/modules/common/gc_enc_8b10b.vhd
+++ b/modules/common/gc_enc_8b10b.vhd
--- a/modules/common/gencores_pkg.vhd
+++ b/modules/common/gencores_pkg.vhd
@@ -78,6 +78,9 @@ package gencores_pkg is
  function to_upper(s : string) return string;
  function to_lower(s : string) return string;

+  -- Bit reversal function
+  function f_reverse_vector (a : in std_logic_vector) return std_logic_vector;
+
  --============================================================================
  -- Component instantiations
  --============================================================================
@@ -1012,4 +1015,17 @@ package body gencores_pkg is
    return lowercase;
  end to_lower;

+  ------------------------------------------------------------------------------
+  -- Vector bit reversal
+  ------------------------------------------------------------------------------
+
+  function f_reverse_vector (a : in std_logic_vector) return std_logic_vector is
+    variable v_result : std_logic_vector(a'reverse_range);
+  begin
+    for i in a'range loop
+      v_result(i) := a(i);
+    end loop;
+    return v_result;
+  end function f_reverse_vector;
+
 end gencores_pkg;