- 25 Feb, 2022 3 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 17 Feb, 2022 2 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 03 Feb, 2022 1 commit
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Tomasz Wlostowski authored
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- 16 Dec, 2021 6 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
Wraps an LM32, DPRAM, UART and indirect memory loader.
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Tomasz Wlostowski authored
inferred_async_fifo: avoid nested 'others' clause in signal initialization to keep ISE (Virtex5) happy
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
modules/dsp: a collection of DSP modules ported from the CommonVisual library. Not yet tested. LICENSING TO BE FIXED!
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- 01 Oct, 2021 1 commit
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Tristan Gingold authored
Add scoped XDC constraints for CDC modules See merge request !16
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- 30 Sep, 2021 1 commit
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Adrian Byszuk authored
These XDC files can be used by Vivado projects to automatically infer proper timing constraints for CDC paths.
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- 29 Sep, 2021 2 commits
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Tristan Gingold authored
Fix reset CDC issue in gc_sync_word_rd See merge request !15
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Tristan Gingold authored
Fix wb_ack_o violation in wb_simple_timer See merge request !14
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- 28 Sep, 2021 2 commits
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Adrian Byszuk authored
The clk_out domain mistakenly used reset from clk_in domain. Additionally, the data_out_o port had this reset signal connected mistakenly as clock enable.
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Adrian Byszuk authored
Fixes issue #29
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- 09 Aug, 2021 1 commit
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Tomasz Wlostowski authored
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- 21 Jan, 2021 1 commit
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Grzegorz Daniluk authored
Logically it's exactly the same, but for some reason Synplify doesn't like "/=" for file opening status.
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- 18 Jan, 2021 1 commit
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Tristan Gingold authored
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- 15 Jan, 2021 1 commit
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Grzegorz Daniluk authored
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- 12 Jan, 2021 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
sim/if_wb_master: fix wb classic broken in commit cbc1c428: [sim] rewrite of the WB master interface
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Grzegorz Daniluk authored
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- 16 Dec, 2020 1 commit
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Tristan Gingold authored
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- 09 Dec, 2020 2 commits
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Tristan Gingold authored
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Tristan Gingold authored
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- 01 Oct, 2020 1 commit
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Grzegorz Daniluk authored
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- 30 Sep, 2020 4 commits
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Tristan Gingold authored
So that in one read access, the software can read both the status and the value and can decide if the value is correct. This avoids race issues.
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Tristan Gingold authored
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Tristan Gingold authored
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Tristan Gingold authored
Simplify the code and avoid possible glitches.
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- 18 Sep, 2020 1 commit
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Olof Kindgren authored
The goal is to make sure that files in the common directory don't depend on things defined elsewhere. With these changes, the only remaining issue is gc_delay_line that uses generic_dpram from genrams Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>
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- 17 Sep, 2020 1 commit
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Tristan Gingold authored
Fixes to the latest proposed_master merge See merge request !11
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- 15 Sep, 2020 3 commits
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Grzegorz Daniluk authored
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Tomasz Wlostowski authored
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Grzegorz Daniluk authored
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- 14 Sep, 2020 2 commits
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Tomasz Wlostowski authored
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Federico Vaga authored
1.1.1 - 2020-09-14 ================== Fixed ----- - sw: fix SPI driver to update the spi_message->actual_length
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