wb_ds182x_readout: also report temperature status in temperature reg

So that in one read access, the software can read both the status and the value and can decide if the value is correct. This avoids race issues.

wb_ds182x_readout: also report temperature status in temperature reg
So that in one read access, the software can read both the status and the value and can decide if the value is correct. This avoids race issues.
4abb522b · Tristan Gingold · 2d716057 · 4abb522b · 4abb522b · 4abb522b
Commit 4abb522b authored Sep 30, 2020 by Tristan Gingold
3 changed files
--- a/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.cheby
+++ b/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.cheby
@@ -21,6 +21,10 @@ memory-map:
        name: data
        description: temperature value
        range: 15-0
+     - field:
+        name: error
+        description: temperature is not valid
+        range: 31
  - reg:
     name: status
     description: status

--- a/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd
+++ b/modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd
-- Do not edit.  Generated on Wed Sep 30 10:51:30 2020 by tgingold
+-- Do not edit.  Generated on Wed Sep 30 11:24:49 2020 by tgingold
 -- With Cheby 1.4.dev0 and these options:
 --  --gen-hdl wb_ds182x_regs.vhd -i wb_ds182x_regs.cheby

@@ -21,6 +21,8 @@ entity wb_ds182x_regs is
    -- temperature
    -- temperature value
    temperature_data_i   : in    std_logic_vector(15 downto 0);
+    -- temperature is not valid
+    temperature_error_i  : in    std_logic;

    -- status
    -- Set when unique id was read
@@ -136,7 +138,7 @@ begin
  end process;

  -- Process for read requests.
-  process (adr_int, rd_req_int, id_i, temperature_data_i, status_id_read_i, status_id_ok_i, status_temp_ok_i) begin
+  process (adr_int, rd_req_int, id_i, temperature_data_i, temperature_error_i, status_id_read_i, status_id_ok_i, status_temp_ok_i) begin
    -- By default ack read requests
    rd_dat_d0 <= (others => 'X');
    case adr_int(3 downto 3) is
@@ -159,7 +161,8 @@ begin
        -- Reg temperature
        rd_ack_d0 <= rd_req_int;
        rd_dat_d0(15 downto 0) <= temperature_data_i;
-        rd_dat_d0(31 downto 16) <= (others => '0');
+        rd_dat_d0(30 downto 16) <= (others => '0');
+        rd_dat_d0(31) <= temperature_error_i;
      when "1" =>
        -- Reg status
        rd_ack_d0 <= rd_req_int;

--- a/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd
+++ b/modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd
@@ -49,6 +49,7 @@ architecture arch of xwb_ds182x_readout is
  signal id_read :  std_logic;                     -- id_o value is valid_o
  signal id_ok   :  std_logic;                    -- Same as id_read_o, but not reset with rst_n_i
  signal temp_ok :  std_logic;
+  signal temp_err : std_logic;
 begin
  i_readout: entity work.gc_ds182x_readout
    generic map (
@@ -65,6 +66,8 @@ begin
      id_read_o => id_read,
      id_ok_o => id_ok);

+  temp_err <= not temp_ok;
+
  i_regs: entity work.wb_ds182x_regs
    port map (
      rst_n_i => rst_n_i,
@@ -74,6 +77,7 @@ begin

      id_i => id,
      temperature_data_i => temper,
+      temperature_error_i => temp_err,
      status_id_read_i => id_read,
      status_id_ok_i => id_ok,
      status_temp_ok_i => temp_ok