Skip to content

P
Platform-independent core collection
Commit 1fac0c87 authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

wb_ds182x_readout: add the temp_ok status bit

parent 1d3abafc
Hide whitespace changes
Inline Side-by-side
Showing with 122 additions and 114 deletions
modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.cheby
View file @ 1fac0c87
......@@ -19,7 +19,7 @@ memory-map:
children:
- field:
name: data
description: temperature
description: temperature value
range: 15-0
- reg:
name: status
......@@ -35,3 +35,7 @@ memory-map:
name: id_ok
description: Set when unique id was read, persist after reset
range: 1
- field:
name: temp_ok
description: Set when the temperature register is correctly read
range: 2
modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd
View file @ 1fac0c87
-- Do not edit. Generated on Wed Sep 30 10:51:30 2020 by tgingold
-- With Cheby 1.4.dev0 and these options:
-- --gen-hdl wb_ds182x_regs.vhd -i wb_ds182x_regs.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
......@@ -14,49 +19,62 @@ entity wb_ds182x_regs is
id_i : in std_logic_vector(63 downto 0);
-- temperature
-- temperature value
temperature_data_i : in std_logic_vector(15 downto 0);
-- status
-- Set when unique id was read
status_id_read_i : in std_logic;
-- Set when unique id was read, persist after reset
status_id_ok_i : in std_logic
status_id_ok_i : in std_logic;
-- Set when the temperature register is correctly read
status_temp_ok_i : in std_logic
);
end wb_ds182x_regs;
architecture syn of wb_ds182x_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal adr_int : std_logic_vector(3 downto 2);
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(3 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
signal wr_sel_d0 : std_logic_vector(3 downto 0);
begin
-- WB decode signals
adr_int <= wb_i.adr(3 downto 2);
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wb_rip <= '0';
elsif rising_edge(clk_i) then
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
rd_req_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wb_wip <= '0';
elsif rising_edge(clk_i) then
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
wr_req_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
......@@ -64,113 +82,96 @@ begin
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_o.dat <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= adr_int;
wr_dat_d0 <= wb_i.dat;
wr_sel_d0 <= wb_i.sel;
end if;
end if;
end process;
-- Register id
-- Register temperature
-- Register status
-- Process for write requests.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wr_ack_int <= '0';
elsif rising_edge(clk_i) then
wr_ack_int <= '0';
case wb_i.adr(3 downto 3) is
when "0" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register id
when "1" =>
-- Register id
when others =>
wr_ack_int <= wr_int;
end case;
when "1" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- Register temperature
when "1" =>
-- Register status
when others =>
wr_ack_int <= wr_int;
end case;
process (wr_adr_d0, wr_req_d0) begin
case wr_adr_d0(3 downto 3) is
when "0" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
-- Reg id
wr_ack_int <= wr_req_d0;
when "1" =>
-- Reg id
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_int;
wr_ack_int <= wr_req_d0;
end case;
end if;
end process;
-- Process for registers read.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
rd_ack1_int <= '0';
reg_rdat_int <= (others => 'X');
elsif rising_edge(clk_i) then
reg_rdat_int <= (others => '0');
case wb_i.adr(3 downto 3) is
when "0" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- id
reg_rdat_int <= id_i(63 downto 32);
rd_ack1_int <= rd_int;
when "1" =>
-- id
reg_rdat_int <= id_i(31 downto 0);
rd_ack1_int <= rd_int;
when others =>
rd_ack1_int <= rd_int;
end case;
when "1" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- temperature
reg_rdat_int(15 downto 0) <= temperature_data_i;
rd_ack1_int <= rd_int;
when "1" =>
-- status
reg_rdat_int(0) <= status_id_read_i;
reg_rdat_int(1) <= status_id_ok_i;
rd_ack1_int <= rd_int;
when others =>
rd_ack1_int <= rd_int;
end case;
when "1" =>
case wr_adr_d0(2 downto 2) is
when "0" =>
-- Reg temperature
wr_ack_int <= wr_req_d0;
when "1" =>
-- Reg status
wr_ack_int <= wr_req_d0;
when others =>
rd_ack1_int <= rd_int;
wr_ack_int <= wr_req_d0;
end case;
end if;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
process (adr_int, rd_req_int, id_i, temperature_data_i, status_id_read_i, status_id_ok_i, status_temp_ok_i) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 3) is
when "0" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- id
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "1" =>
-- id
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_dat_d0 <= (others => 'X');
case adr_int(3 downto 3) is
when "0" =>
case adr_int(2 downto 2) is
when "0" =>
-- Reg id
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= id_i(63 downto 32);
when "1" =>
-- Reg id
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= id_i(31 downto 0);
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "1" =>
case wb_i.adr(2 downto 2) is
when "0" =>
-- temperature
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "1" =>
-- status
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "1" =>
case adr_int(2 downto 2) is
when "0" =>
-- Reg temperature
rd_ack_d0 <= rd_req_int;
rd_dat_d0(15 downto 0) <= temperature_data_i;
rd_dat_d0(31 downto 16) <= (others => '0');
when "1" =>
-- Reg status
rd_ack_d0 <= rd_req_int;
rd_dat_d0(0) <= status_id_read_i;
rd_dat_d0(1) <= status_id_ok_i;
rd_dat_d0(2) <= status_temp_ok_i;
rd_dat_d0(31 downto 3) <= (others => '0');
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd
View file @ 1fac0c87
......@@ -48,6 +48,7 @@ architecture arch of xwb_ds182x_readout is
signal temper : std_logic_vector(15 downto 0); -- temperature value (refreshed every second)
signal id_read : std_logic; -- id_o value is valid_o
signal id_ok : std_logic; -- Same as id_read_o, but not reset with rst_n_i
signal temp_ok : std_logic;
begin
i_readout: entity work.gc_ds182x_readout
generic map (
......@@ -60,19 +61,21 @@ begin
onewire_b => onewire_b,
id_o => id,
temper_o => temper,
temp_ok_o => temp_ok,
id_read_o => id_read,
id_ok_o => id_ok);
i_regs: entity work.wb_ds182x_regs
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
wb_i => wb_i,
wb_o => wb_o,
id_i => id,
temperature_data_i => temper,
status_id_read_i => id_read,
status_id_ok_i => id_ok
status_id_ok_i => id_ok,
status_temp_ok_i => temp_ok
);
end arch;
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment