modules/common: added 'slow clock'/strobe pulse generator module. LICENSING TO BE FIXED

4ef4d9d1 · Tomasz Wlostowski · 62668620 · 4ef4d9d1 · 4ef4d9d1
Commit 4ef4d9d1 authored Dec 16, 2021 by Tomasz Wlostowski
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Manifest.py modules/common/Manifest.py +1 -0

gc_slow_clock_gen.vhd modules/common/gc_slow_clock_gen.vhd +60 -0

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--- a/modules/common/Manifest.py
+++ b/modules/common/Manifest.py
@@ -42,4 +42,5 @@ files = [
    "gc_async_counter_diff.vhd",
    "gc_sync_word_wr.vhd",
    "gc_sync_word_rd.vhd",
+    "gc_slow_clock_gen.vhd"
 ];
--- a/modules/common/gc_slow_clock_gen.vhd
+++ b/modules/common/gc_slow_clock_gen.vhd
+------------------------------------------
+------------------------------------------
+-- Date        : Fri Aug 21 14:48:22 2015
+--
+-- Author      : Daniel Valuch
+--
+-- Company     : CERN BE/RF/FB
+--
+-- Description : Function rise/fall speed limiter
+--
+------------------------------------------
+------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+
+entity gc_slow_clock_gen is
+  generic (
+    -- number of data bits
+    g_DATA_BITS : positive := 16
+    );
+  port (
+    clk_i : in std_logic;
+    rst_i : in std_logic;
+
+    enable_i       : in  std_logic;
+    rate_divider_i : in  std_logic_vector(15 downto 0);
+    tick_o         : out std_logic
+    );
+end gc_slow_clock_gen;
+
+architecture rtl of gc_slow_clock_gen is
+
+  signal rate_cnt  : unsigned(15 downto 0);
+  signal rate_tick : std_logic;
+
+begin
+
+  p_gen_rate : process(clk_i, rst_i)
+  begin
+    if rst_i = '1' then
+      rate_cnt  <= unsigned(rate_divider_i);
+      rate_tick <= '0';
+    elsif enable_i = '1' then
+      if rate_cnt = 0 then
+        rate_cnt  <= unsigned(rate_divider_i);
+        rate_tick <= '1';
+      else
+        rate_cnt <= rate_cnt - 1;
+      end if;
+    else
+      rate_tick <= '0';
+    end if;
+  end process;
+
+  tick_o <= rate_tick;
+end rtl;