wb_simple_timer module has ACC output that is tied to '1':
wb_ack_o <= '1';
This is violation of Wishbone B.4 specification rules 3.35 and 3.50.
As a minimum, this signal should be wired as wb_ack_o <= wb_stb_i and wb_cyc_i, which is allowed.

This is a real problem because this slave breaks some simulation drivers, for example Vunit Wishbone VC.