Commit a68a932b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wb_fine_pulse_gen: fix incorrect reset signal for IDELAYCTRL for Ultrascale devices

parent 605b1e25
......@@ -165,7 +165,7 @@ begin
port map (
RDY => odelayctrl_rdy_o,
REFCLK => clk_odelay,
RST => odelayctrl_rst_i
RST => rst_synced
end block;
end generate gen_use_odelay;
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