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Platform-independent core collection
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Platform-independent core collection
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a68a932b
Commit
a68a932b
authored
Aug 09, 2021
by
Tomasz Wlostowski
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wb_fine_pulse_gen: fix incorrect reset signal for IDELAYCTRL for Ultrascale devices
parent
605b1e25
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fine_pulse_gen_kintexultrascale_shared.vhd
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modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
View file @
a68a932b
...
...
@@ -165,7 +165,7 @@ begin
port
map
(
RDY
=>
odelayctrl_rdy_o
,
REFCLK
=>
clk_odelay
,
RST
=>
odelayctrl_rst_i
RST
=>
rst_synced
);
end
block
;
end
generate
gen_use_odelay
;
...
...
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