- Rework simdrv_defs into a package
- Use SV queues instead of dynamic arrays in the APIs (as they resemble C++'s std::vector a bit more, hence are more convenient to use)
- Added AXI4 BFMs from the PULP project library
- Added a bunch of simulation drivers (for the VUART & LM32 MCS cores)
- Added a trivial unit test/logging "framework" (logger.svh)

Note these changes will break your legacy testbenches, here's how to fix the most common issues:
- Replace the includes of simdrv_defs.svh indo an include of "gencores_sim_defs.svh" followed by
  import of gencores_sim_pkg package
- If your code uses CBusAccessor::readm/writem, change the addr/data parameters to use SV queues instead of dynamic arrays

Issue occurred when "wb.ack" became active in the same cycle as "wb.stall" became inactive. The "RESPONSE_READ" state was skipped and therefore a proper handshake with the axilite bus wasn't guaranteed.

hdl/sim: Protect CIWBMasterAccessor against multiple requests

See merge request !19

When performing reads/writes from multiple threads, CIWBMasterAccessor does not provide any
protection, leading to data from one request being delivered to another.

By replacing the data queues with SV mailboxes, we ensure that only one thread can access the
mailbox at any given time. Furthermore, we add a SV event in wb_cycle_t, which is used to notify
the readm()/writem() tasks that their transfer is complete, to avoid getting the result of the
wrong transfer.

components purely dependent of xilinx libraries are not compiled in if
target differs from xilinx

Needed to fix fmc-adc channel always 0 issue

Add scoped XDC constraints for CDC modules

See merge request !16

These XDC files can be used by Vivado projects to automatically infer
proper timing constraints for CDC paths.

Fix reset CDC issue in gc_sync_word_rd

See merge request !15

Fix wb_ack_o violation in wb_simple_timer

See merge request !14

The clk_out domain mistakenly used reset from clk_in domain.
Additionally, the data_out_o port had this reset signal connected mistakenly as clock enable.

Fixes issue #29

Logically it's exactly the same, but for some reason Synplify doesn't
like "/=" for file opening status.

sim/if_wb_master: fix wb classic broken in commit cbc1c428: [sim] rewrite of the WB master interface