sim: regenerated PWM & UART IP registers for SV simulation models

3e297837 · Tomasz Wlostowski · 37571aa1 · 3e297837 · 3e297837
Commit 3e297837 authored Dec 15, 2022 by Tomasz Wlostowski
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spwm_regs.vh sim/regs/spwm_regs.vh +16 -0

wb_uart_regs.vh sim/regs/wb_uart_regs.vh +43 -0

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--- a/sim/regs/spwm_regs.vh
+++ b/sim/regs/spwm_regs.vh
+`define ADDR_SPWM_CR                   6'h0
+`define SPWM_CR_PRESC_OFFSET 0
+`define SPWM_CR_PRESC 32'h0000ffff
+`define SPWM_CR_PERIOD_OFFSET 16
+`define SPWM_CR_PERIOD 32'hffff0000
+`define ADDR_SPWM_SR                   6'h4
+`define SPWM_SR_N_CHANNELS_OFFSET 0
+`define SPWM_SR_N_CHANNELS 32'h0000000f
+`define ADDR_SPWM_DR0                  6'h8
+`define ADDR_SPWM_DR1                  6'hc
+`define ADDR_SPWM_DR2                  6'h10
+`define ADDR_SPWM_DR3                  6'h14
+`define ADDR_SPWM_DR4                  6'h18
+`define ADDR_SPWM_DR5                  6'h1c
+`define ADDR_SPWM_DR6                  6'h20
+`define ADDR_SPWM_DR7                  6'h24
--- a/sim/regs/wb_uart_regs.vh
+++ b/sim/regs/wb_uart_regs.vh
+`define ADDR_UART_SR                   5'h0
+`define UART_SR_TX_BUSY_OFFSET 0
+`define UART_SR_TX_BUSY 32'h00000001
+`define UART_SR_RX_RDY_OFFSET 1
+`define UART_SR_RX_RDY 32'h00000002
+`define UART_SR_RX_FIFO_SUPPORTED_OFFSET 2
+`define UART_SR_RX_FIFO_SUPPORTED 32'h00000004
+`define UART_SR_TX_FIFO_SUPPORTED_OFFSET 3
+`define UART_SR_TX_FIFO_SUPPORTED 32'h00000008
+`define UART_SR_RX_FIFO_VALID_OFFSET 4
+`define UART_SR_RX_FIFO_VALID 32'h00000010
+`define UART_SR_TX_FIFO_EMPTY_OFFSET 5
+`define UART_SR_TX_FIFO_EMPTY 32'h00000020
+`define UART_SR_TX_FIFO_FULL_OFFSET 6
+`define UART_SR_TX_FIFO_FULL 32'h00000040
+`define UART_SR_RX_FIFO_OVERFLOW_OFFSET 7
+`define UART_SR_RX_FIFO_OVERFLOW 32'h00000080
+`define UART_SR_RX_FIFO_BYTES_OFFSET 8
+`define UART_SR_RX_FIFO_BYTES 32'h0000ff00
+`define ADDR_UART_BCR                  5'h4
+`define ADDR_UART_TDR                  5'h8
+`define UART_TDR_TX_DATA_OFFSET 0
+`define UART_TDR_TX_DATA 32'h000000ff
+`define ADDR_UART_RDR                  5'hc
+`define UART_RDR_RX_DATA_OFFSET 0
+`define UART_RDR_RX_DATA 32'h000000ff
+`define ADDR_UART_HOST_TDR             5'h10
+`define UART_HOST_TDR_DATA_OFFSET 0
+`define UART_HOST_TDR_DATA 32'h000000ff
+`define UART_HOST_TDR_RDY_OFFSET 8
+`define UART_HOST_TDR_RDY 32'h00000100
+`define ADDR_UART_HOST_RDR             5'h14
+`define UART_HOST_RDR_DATA_OFFSET 0
+`define UART_HOST_RDR_DATA 32'h000000ff
+`define UART_HOST_RDR_RDY_OFFSET 8
+`define UART_HOST_RDR_RDY 32'h00000100
+`define UART_HOST_RDR_COUNT_OFFSET 9
+`define UART_HOST_RDR_COUNT 32'h01fffe00
+`define ADDR_UART_CR                   5'h18
+`define UART_CR_RX_FIFO_PURGE_OFFSET 0
+`define UART_CR_RX_FIFO_PURGE 32'h00000001
+`define UART_CR_TX_FIFO_PURGE_OFFSET 1
+`define UART_CR_TX_FIFO_PURGE 32'h00000002