gc_pulse_syncrhonizer2: use reset for the internal state

Needed to fix fmc-adc channel always 0 issue

gc_pulse_syncrhonizer2: use reset for the internal state
Needed to fix fmc-adc channel always 0 issue
a0aeffbb · Tristan Gingold · 7d76d2b6 · a0aeffbb
Commit a0aeffbb authored May 31, 2022 by Tristan Gingold
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gc_pulse_synchronizer2.vhd modules/common/gc_pulse_synchronizer2.vhd +31 -24

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--- a/modules/common/gc_pulse_synchronizer2.vhd
+++ b/modules/common/gc_pulse_synchronizer2.vhd
@@ -89,31 +89,38 @@ begin  -- rtl
  p_input_ack : process(clk_in_i)
  begin
    if rising_edge(clk_in_i) then
-
-      d_p_d0   <= d_p_i;
-      d_ack_d0 <= d_ack;
-
-      if ready = '1' and d_p_i = '1' and d_p_d0 = '0'then
-        --  Incoming pulse detected and the system is ready.
-        --  Transfer it.
-        in_ext <= '1';
-        --  Clear ack and ready!
-        d_ack  <= '0';
-        ready  <= '0';
-      elsif in_ext = '1' and out_feedback = '1' then
-        --  Pulse has been transfered, clear the input.
-        in_ext <= '0';
-      elsif in_ext = '0' and out_feedback = '0' then
-        --  Clear transfered.  Done.
-        --  This is also the steady state.
-        d_ack <= '1';
+      if rst_in_n_i = '0' then
+        d_p_d0 <= '0';
+        d_ack <= '0';
+        d_ack_d0 <= '0';
        ready <= '1';
-      end if;
-
-      if ready = '0' then
-        assert d_p_i = '0' or (d_p_i = '1' and d_p_d0 = '1')
-          report "request while previous one not completed"
-          severity ERROR;
+        in_ext <= '0';
+      else
+        d_p_d0   <= d_p_i;
+        d_ack_d0 <= d_ack;
+
+        if ready = '1' and d_p_i = '1' and d_p_d0 = '0'then
+          --  Incoming pulse detected and the system is ready.
+          --  Transfer it.
+          in_ext <= '1';
+          --  Clear ack and ready!
+          d_ack  <= '0';
+          ready  <= '0';
+        elsif in_ext = '1' and out_feedback = '1' then
+          --  Pulse has been transfered, clear the input.
+          in_ext <= '0';
+        elsif in_ext = '0' and out_feedback = '0' then
+          --  Clear transfered.  Done.
+          --  This is also the steady state.
+          d_ack <= '1';
+          ready <= '1';
+        end if;
+
+        if ready = '0' then
+          assert d_p_i = '0' or (d_p_i = '1' and d_p_d0 = '1')
+            report "request while previous one not completed"
+            severity ERROR;
+        end if;
      end if;
    end if;
  end process p_input_ack;