Wraps an LM32, DPRAM, UART and indirect memory loader.

inferred_async_fifo: avoid nested 'others' clause in signal initialization to keep ISE (Virtex5) happy

modules/dsp: a collection of DSP modules ported from the CommonVisual library. Not yet tested. LICENSING TO BE FIXED!

Add scoped XDC constraints for CDC modules

See merge request !16

These XDC files can be used by Vivado projects to automatically infer
proper timing constraints for CDC paths.

Fix reset CDC issue in gc_sync_word_rd

See merge request !15

Fix wb_ack_o violation in wb_simple_timer

See merge request !14

The clk_out domain mistakenly used reset from clk_in domain.
Additionally, the data_out_o port had this reset signal connected mistakenly as clock enable.

Fixes issue #29

Logically it's exactly the same, but for some reason Synplify doesn't
like "/=" for file opening status.

sim/if_wb_master: fix wb classic broken in commit cbc1c428: [sim] rewrite of the WB master interface

So that in one read access, the software can read both the status and
the value and can decide if the value is correct.  This avoids race
issues.

Simplify the code and avoid possible glitches.

The goal is to make sure that files in the common directory don't
depend on things defined elsewhere. With these changes, the only
remaining issue is gc_delay_line that uses generic_dpram from
genrams
Signed-off-by: Olof Kindgren <olof.kindgren@gmail.com>

Fixes to the latest proposed_master merge

See merge request !11