By using altsyncram directly, we get the follow benefits:
  * clear control of read-write resolution behaviour
  * can specify a mif file for initialization
  * eliminates warnings about dual-port clock inference timings

Unfortunately, Arria5 cannot do read-old-data for the same port.
This formulation describes a dual-ported RAM with:
  write-first/read-new-data for RW conflict on same port
  read-first /read-old-data for RW conflict between ports
... which is exactly what Arria5 supports (and Arria2 can do too).

Users of the generic_dpram should simply avoid simultaneous
RW on the same port, as the result is undefined (Altera != Xilinx).

Newer quartus versions recognized that the code describes write-first logic,
which requires combinatorial bypass logic. Unfortunately, this is also impossible
with two clocks. Thus they reject synthesis. This manifests as the WR endpoint
RX path failing to synthesize.

This is the equivalent of commit 53979d4f.

I have no idea why.

With 63, no dual port memory is inferred.
With 7, it all works peachy.

Why on earth it affects completely independent code I cannot explain.

genrams: increased width of internal byte select array to avoid compilation/synthesis errors on rams wider than 64 bits

Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago

Genrams is a collection of synthesizable RAM/FIFO providing identical interface and features on different FPGA platforms.

Quartus will not process a 'file_open' call during synthesis,
so we can instead initialize the RAM with a vhdl constant.