genrams: fixed wrong bwsel port size when data width is not a multiple of 8
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- modules/genrams/altera/generic_dpram.vhd 3 additions, 3 deletionsmodules/genrams/altera/generic_dpram.vhd
- modules/genrams/altera/generic_spram.vhd 1 addition, 1 deletionmodules/genrams/altera/generic_spram.vhd
- modules/genrams/genram_pkg.vhd 3 additions, 3 deletionsmodules/genrams/genram_pkg.vhd
- modules/genrams/xilinx/generic_dpram.vhd 5 additions, 5 deletionsmodules/genrams/xilinx/generic_dpram.vhd
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