Unfortunately, Arria5 cannot do read-old-data for the same port.
This formulation describes a dual-ported RAM with:
  write-first/read-new-data for RW conflict on same port
  read-first /read-old-data for RW conflict between ports
... which is exactly what Arria5 supports (and Arria2 can do too).

Users of the generic_dpram should simply avoid simultaneous
RW on the same port, as the result is undefined (Altera != Xilinx).