altera dpram: quell modelsim warning

modules/genrams/altera/generic_async_fifo.vhd

@@ -115,7 +115,7 @@ architecture syn of generic_async_fifo is
       q       : out std_logic_vector (g_data_width-1 downto 0);
       wrreq   : in  std_logic;
       data    : in  std_logic_vector (g_data_width-1 downto 0);
-      wrusedw : out std_logic_vector (f_log2_size(g_size)-1downto 0);
+      wrusedw : out std_logic_vector (f_log2_size(g_size)-1 downto 0);
       rdusedw : out std_logic_vector (f_log2_size(g_size)-1 downto 0)
       );
   end component;

modules/genrams/altera/generic_dpram.vhd

@@ -79,6 +79,7 @@ architecture syn of generic_dpram is
       return "DONT_CARE";
     else
       assert (false) report "generic_dpram: g_addr_conflict_resolution must be: read_first, write_first, dont_care" severity failure;
+      return "DONT_CARE";
     end if;
   end f_sameport_order;
   
@@ -92,6 +93,7 @@ architecture syn of generic_dpram is
       return "DONT_CARE";
     else
       assert (false) report "generic_dpram: g_addr_conflict_resolution must be: read_first, write_first, dont_care" severity failure;
+      return "DONT_CARE";
     end if;
   end f_diffport_order;
   

modules/genrams/altera/generic_simple_dpram.vhd

@@ -69,6 +69,7 @@ architecture syn of generic_simple_dpram is
       return "DONT_CARE";
     else
       assert (false) report "generic_simple_dpram: g_addr_conflict_resolution must be: read_first, write_first, dont_care" severity failure;
+      return "DONT_CARE";
     end if;
   end f_diffport_order;
   

modules/genrams/altera/generic_spram.vhd

@@ -63,6 +63,7 @@ architecture syn of generic_spram is
       return "DONT_CARE";
     else
       assert (false) report "generic_spram: g_addr_conflict_resolution must be: read_first, write_first, dont_care" severity failure;
+      return "DONT_CARE";
     end if;
   end f_sameport_order;