This is beneficial because the gc_sync_ffs has a Xilinx "keep" attribute, which prevents the tools
from trimming out unused logic, even when the user has set the relevant generics to "FALSE".

genrams: when pre-loading a RAM with an init file, assert that the file size is not bigger than the size of the memory it is written to

genrams: when pre-loading a RAM with an init file, assert that the file size is not bigger than the size of the memory it is written to

The previous implementation was introducing latches to the GN4124 core under Xilinx ISE.

Tested and verified to work with the following SPEC-based reference designs:
 - WR
 - MT
 - WRTD

genram: automatically pad with zeroes when reading from a mem init file smaller than the memory itself

They finally don't help much and they break simulation as Modelsim complains
about types conversion.

Maciej Lipinski authored 7 years ago and Grzegorz Daniluk committed 7 years ago

it was de-asserted at wrong value (too early/late). This was making
to misbehave the modules that depend on this signals.

New function expects textfile with binary representation of each word in a
separate line, e.g.:
10011000000000000000000000000000
11010000000000000000000000000000
11010000001000000000000000000000
01111000000000010000000000000000
00111000001000010000000000000000

This for example reduces WRPC SPEC reference design synthesis time from ~26
minutes to ~11 minutes.

The so-called "inferred_X_fifo" are basically generics fifos using
inferred rams blocks from altera or xilinx, depending the target
platform. That's why it makes more sense to move them to the "generic"
folder of genrams. This change forces to rename the "generic_X_fifo"
under "altera". Since these fifos are using the altera fifo  Megafunction,
are going to be called "altera_X_fifo". The Manifest has been changed accordingly.

Peter Jansweijer authored 11 years ago and Grzegorz Daniluk committed 10 years ago

The simulator is crashing at the end of the LM32 startup code when it tries to
access the highest RAM location (at the stack pointer). After this access, the
LM32 verilog code already increments the address to be prepared for the next
cycle, which will never actually happen because you are at the end of the RAM.
It is this address increment in verilog that is one address outside the defined
RAM array for which the simulator complains and terminates. The actual
synthesized code is perfectly fine; no accesses outside RAM.

FIFO counters to other clock domain. Allows to constrain the maximum sync chain delay in a single UCF line.