- 28 Sep, 2019 1 commit
-
-
Dimitris Lampridis authored
-
- 27 Sep, 2019 3 commits
-
-
Dimitris Lampridis authored
-
Dimitris Lampridis authored
-
Dimitris Lampridis authored
-
- 26 Sep, 2019 5 commits
-
-
Dimitris Lampridis authored
-
Dimitris Lampridis authored
-
Dimitris Lampridis authored
-
Dimitris Lampridis authored
-
Dimitris Lampridis authored
-
- 24 May, 2019 3 commits
-
-
Dimitris Lampridis authored
The following changes were done: 1. Point all submodules to new OHWR 2. update ddr3-sp6-core to latest master because the previous commit (8618c1e154c322be34cb069b62d8293527744dda) was not available in OHWR. Please test! 3. remove etherbone-core 4. update general-cores to latest master and use the updated gc_ds182x_readout module
-
Dimitris Lampridis authored
-
Dimitris Lampridis authored
-
- 21 Sep, 2018 7 commits
-
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
- 17 Sep, 2018 3 commits
-
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
- 16 Sep, 2018 5 commits
-
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
fmc_tdc_core: treat int_flag_i as a synchronous signal, added an IODELAY line programmable from the host to adjust the timing. Possible fix for the 131us bug
-
Tomasz Wlostowski authored
hdl: don't use the clks_rsts_manager state machine for driving WR DAC, use standard WR dac interface instead
-
Tomasz Wlostowski authored
-
- 12 Sep, 2018 2 commits
-
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timing
-
- 11 Sep, 2018 9 commits
-
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timing
-
- 07 Sep, 2018 1 commit
-
-
Tristan Gingold authored
From Tom's dma branch.
-
- 04 Sep, 2018 1 commit
-
-
Tristan Gingold authored
-