- 24 Oct, 2020 1 commit
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David Cussans authored
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- 22 Oct, 2020 1 commit
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David Cussans authored
Removing TLU manual from Firm(Gate)ware repository. The definitive version is in the 'toplevel' repo: https://ohwr.org/project/fmc-mtlu
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- 20 Oct, 2020 9 commits
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David Cussans authored
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David Cussans authored
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David Cussans authored
Dcussans/update docs See merge request !5
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David Cussans authored
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David Cussans authored
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David Cussans authored
Dcussans/add ipbus decode tl uaddrmap See merge request !4
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David Cussans authored
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David Cussans authored
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David Cussans authored
Large number of conflicts reports - but almost all of these seem to have been white-space only README.md conflict probably not resolved correctly. Tidying up some files. This seems to have resulted in conflict with master, but I don't know how.
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- 02 Sep, 2020 4 commits
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David Cussans authored
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David Cussans authored
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David Cussans authored
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David Cussans authored
Merging changes back to master. Seems to be in a state where the permissions were wrong. Creating a new branch to merge back to master
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- 13 May, 2020 2 commits
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David Cussans authored
Dcussans/8bit fine ts See merge request !2
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David Cussans authored
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- 03 Mar, 2020 1 commit
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David Cussans authored
generate_bfm_input - text fed into HREAD must be long enough to fill variable ( e.g. HREAD into 32 bit integer needs 8 chars ) dualSERDES_1to_4 - changed delay on delayed IDELAYE2 in order to balance up delays triggerInputs_newTLU - fixed bug in code to swap between rising and falling edges TLUaddrmap.xml - added new register for optional invert edge selection. transactionGenerator_behavioural.vhd - simulation should now finish cleanly, rather than hanging in loop
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- 02 Mar, 2020 3 commits
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David Cussans authored
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David Cussans authored
Inspection "by eye" shows linear correlation between delay of pulse and fine-grain timestamp.
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David Cussans authored
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- 28 Feb, 2020 1 commit
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David Cussans authored
Use AIDA_tlu/components/tlu/sim/cfg/triggerInputs_newTLU_tb.dep to build with ipbb
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- 25 Feb, 2020 7 commits
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David Cussans authored
This led to some minor changes to logic_clocks. Hopefully making it more robust...
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David Cussans authored
Fixing typo in process sensitivity list in logic_clocks. Hopefully won't have affected function ....
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David Cussans authored
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David Cussans authored
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David Cussans authored
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David Cussans authored
Dcussans/ipbus1v6 update See merge request !1
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David Cussans authored
Removing unused files.
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- 24 Feb, 2020 3 commits
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David Cussans authored
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David Cussans authored
Should now build against IPBus v1.6
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David Cussans authored
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- 04 Jul, 2019 2 commits
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Paolo Baesso authored
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Paolo Baesso authored
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- 26 Apr, 2019 4 commits
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David Cussans authored
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David Cussans authored
* Incrementing version number ( now v24 )
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David Cussans authored
* Removed unused code and signals. * Changed way strobes are generated - use 40MHz clock as input. (Should be much more robust than previous mechanism) Incremented version number to 23
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- 17 Apr, 2019 2 commits
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David Cussans authored
deleting pc051a_infra_sim.{dep,vhd} - these files were never needed deleting enclustra_ax3_pm3_infra.patch - made a copy, so don't need to patch deleting enclustra_ax3_pm3_infra.vhd - duplicate copy
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David Cussans authored
triggerLogic_rtl.vhd - changed not to need VHDL-2008 tlu_1e.dep - changed to correct order to work with ipbb sim. Added VHDL-2008 flags top_tim.dep - top level dep file to build simulation infra_sim.vhd - infrastructure ( Ethernet Mac + IPBus control ) for simulation. IPBB not able to ignore synthesis only files
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