@@ -143,7 +143,7 @@ We can now define the trigger logic to be used to assert a valid trigger: we onl
\end{itemize}
\section{Stretch and delay}
The trigger logic is designed to detect edge transitions\footnote{Currently only negative edges are registered. A future firmware version will implement user-selectable positive or negative edge detection.} at the trigger inputs and produce a pulse for each transition detected. The pulse has an initial duration of one clock cycle (f= 160~MHz, one cycle 6.25~ns) and occurs on the next rising edge of the 160~MHz internal clock.\\
The trigger logic is designed to detect edge transitions\footnote{By default transitions from low voltage to high voltage are detected (e.g. the leading edge of TTL pulses). The bottom 6 bits of \gls{ipbus} register InvertEdgeW can be used to select triggering on high voltage to low voltage transitions (e.g. NIM pulses, PMT pulses)} at the trigger inputs and produce a pulse for each transition detected. The internal pulse has an initial duration of one clock cycle (f= 160~MHz, one cycle 6.25~ns) and occurs on the next rising edge of the 160~MHz internal clock.\\
Each pulse can be stretched and delayed in integer numbers of clock cycles to compensate for differences in cable length. Two separate 5-bit registers are used for the task: the value written in the registers will stretch/delay the pulse by a corresponding number of clock cycles.\\
Diagram~\ref{Fig:trigger_stretchdelay} shows the effect of the delay and stretch words on the trigger logic.
\begin{figure}
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@@ -153,4 +153,4 @@ Diagram~\ref{Fig:trigger_stretchdelay} shows the effect of the delay and stretch
\caption{Effect of the stretch and delay values. In1 is delayed by 2 clock cycles (t1= 12.5~ns) and stretched by 5 clock cycles (t2= 31.25~ns) to create a coincidence window with in5 and produce the resulting trigger signal.}
\label{Fig:trigger_stretchdelay}
\end{figure}\\
Further details on how to configure the stretch and delay values are provided in section~\ref{ch:EUDAQPar}.
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Further details on how to configure the stretch and delay values are provided in section~\ref{ch:EUDAQPar}.
