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AIDA-2020 TLU - Gateware
Commits
678b4c67
Commit
678b4c67
authored
Feb 25, 2020
by
David Cussans
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Minor tweaks to build script. Some tidying up.
Removing unused files.
parent
98468998
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6 changed files
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8 additions
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328 deletions
+8
-328
enclustra_ax3_pm3_infra-example.vhd
...fw/synth/firmware/hdl/enclustra_ax3_pm3_infra-example.vhd
+0
-137
top_enclustra_ax3_pm3.vhd
..._pm3/base_fw/synth/firmware/hdl/top_enclustra_ax3_pm3.vhd
+0
-83
enclustra_ax3_pm3.patch
...x3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch
+0
-36
enclustra_ax3_pm3.tcl.sav
..._pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl.sav
+0
-55
TLU_enclustra_v1e_setProcessingOrder.tcl
...v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl
+0
-11
build_tlu_firmware.sh
AIDA_tlu/scripts/build_tlu_firmware.sh
+8
-6
No files found.
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra-example.vhd
deleted
100644 → 0
View file @
98468998
-- enclustra_ax3_pm3_infra
--
-- Example "infra" file.
-- DO NOT USE THIS FILE.
-- Use the "patch" file to patch enclustra_ax3_pm3_infra.vhd in
-- ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl
-- David Cussans, January 2019
--
-- Original:
-- Dave Newbold, June 2013
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
work
.
ipbus
.
all
;
entity
enclustra_ax3_pm3_infra
is
port
(
sysclk
:
in
std_logic
;
-- 50MHz board crystal clock
clk_ipb_o
:
out
std_logic
;
-- IPbus clock
rst_ipb_o
:
out
std_logic
;
clk125_o
:
out
std_logic
;
rst125_o
:
out
std_logic
;
clk_aux_o
:
out
std_logic
;
-- 50MHz clock
rst_aux_o
:
out
std_logic
;
nuke
:
in
std_logic
;
-- The signal of doom
soft_rst
:
in
std_logic
;
-- The signal of lesser doom
leds
:
out
std_logic_vector
(
1
downto
0
);
-- status LEDs
rgmii_txd
:
out
std_logic_vector
(
3
downto
0
);
rgmii_tx_ctl
:
out
std_logic
;
rgmii_txc
:
out
std_logic
;
rgmii_rxd
:
in
std_logic_vector
(
3
downto
0
);
rgmii_rx_ctl
:
in
std_logic
;
rgmii_rxc
:
in
std_logic
;
mac_addr
:
in
std_logic_vector
(
47
downto
0
);
-- MAC address
ip_addr
:
in
std_logic_vector
(
31
downto
0
);
-- IP address
ipb_in
:
in
ipb_rbus
;
-- ipbus
ipb_out
:
out
ipb_wbus
);
end
enclustra_ax3_pm3_infra
;
architecture
rtl
of
enclustra_ax3_pm3_infra
is
signal
clk125_fr
,
clk125
,
clk125_90
,
clk200
,
clk_ipb
,
clk_ipb_i
,
locked
,
rst125
,
rst_ipb
,
rst_ipb_ctrl
,
rst_eth
,
onehz
,
pkt
:
std_logic
;
signal
mac_tx_data
,
mac_rx_data
:
std_logic_vector
(
7
downto
0
);
signal
mac_tx_valid
,
mac_tx_last
,
mac_tx_error
,
mac_tx_ready
,
mac_rx_valid
,
mac_rx_last
,
mac_rx_error
:
std_logic
;
signal
led_p
:
std_logic_vector
(
0
downto
0
);
begin
-- DCM clock generation for internal bus, ethernet
clocks
:
entity
work
.
clocks_7s_extphy_se
port
map
(
sysclk
=>
sysclk
,
clko_125
=>
clk125
,
clko_125_90
=>
clk125_90
,
clko_200
=>
clk200
,
clko_ipb
=>
clk_ipb_i
,
locked
=>
locked
,
nuke
=>
nuke
,
soft_rst
=>
soft_rst
,
rsto_125
=>
rst125
,
rsto_ipb
=>
rst_ipb
,
rsto_ipb_ctrl
=>
rst_ipb_ctrl
,
onehz
=>
onehz
);
clk_ipb
<=
clk_ipb_i
;
-- Best to align delta delays on all clocks for simulation
clk_ipb_o
<=
clk_ipb_i
;
rst_ipb_o
<=
rst_ipb
;
clk125_o
<=
clk125
;
rst125_o
<=
rst125
;
stretch
:
entity
work
.
led_stretcher
generic
map
(
WIDTH
=>
1
)
port
map
(
clk
=>
clk125
,
d
(
0
)
=>
pkt
,
q
=>
led_p
);
leds
<=
(
led_p
(
0
),
locked
and
onehz
);
-- Ethernet MAC core and PHY interface
eth
:
entity
work
.
eth_7s_rgmii
port
map
(
clk125
=>
clk125
,
clk125_90
=>
clk125_90
,
clk200
=>
clk200
,
rst
=>
rst125
,
rgmii_txd
=>
rgmii_txd
,
rgmii_tx_ctl
=>
rgmii_tx_ctl
,
rgmii_txc
=>
rgmii_txc
,
rgmii_rxd
=>
rgmii_rxd
,
rgmii_rx_ctl
=>
rgmii_rx_ctl
,
rgmii_rxc
=>
rgmii_rxc
,
tx_data
=>
mac_tx_data
,
tx_valid
=>
mac_tx_valid
,
tx_last
=>
mac_tx_last
,
tx_error
=>
mac_tx_error
,
tx_ready
=>
mac_tx_ready
,
rx_data
=>
mac_rx_data
,
rx_valid
=>
mac_rx_valid
,
rx_last
=>
mac_rx_last
,
rx_error
=>
mac_rx_error
);
-- ipbus control logic
ipbus
:
entity
work
.
ipbus_ctrl
port
map
(
mac_clk
=>
clk125
,
rst_macclk
=>
rst125
,
ipb_clk
=>
clk_ipb
,
rst_ipb
=>
rst_ipb_ctrl
,
mac_rx_data
=>
mac_rx_data
,
mac_rx_valid
=>
mac_rx_valid
,
mac_rx_last
=>
mac_rx_last
,
mac_rx_error
=>
mac_rx_error
,
mac_tx_data
=>
mac_tx_data
,
mac_tx_valid
=>
mac_tx_valid
,
mac_tx_last
=>
mac_tx_last
,
mac_tx_error
=>
mac_tx_error
,
mac_tx_ready
=>
mac_tx_ready
,
ipb_out
=>
ipb_out
,
ipb_in
=>
ipb_in
,
mac_addr
=>
mac_addr
,
ip_addr
=>
ip_addr
,
pkt
=>
pkt
);
end
rtl
;
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/top_enclustra_ax3_pm3.vhd
deleted
100644 → 0
View file @
98468998
-- Top-level design for ipbus demo
--
-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
--
-- You must edit this file to set the IP and MAC addresses
--
-- Dave Newbold, 4/10/16
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
ALL
;
use
work
.
ipbus
.
ALL
;
entity
top
is
port
(
sysclk
:
in
std_logic
;
leds
:
out
std_logic_vector
(
3
downto
0
);
-- status LEDs
cfg
:
in
std_logic_vector
(
3
downto
0
);
-- switches
rgmii_txd
:
out
std_logic_vector
(
3
downto
0
);
rgmii_tx_ctl
:
out
std_logic
;
rgmii_txc
:
out
std_logic
;
rgmii_rxd
:
in
std_logic_vector
(
3
downto
0
);
rgmii_rx_ctl
:
in
std_logic
;
rgmii_rxc
:
in
std_logic
;
phy_rstn
:
out
std_logic
);
end
top
;
architecture
rtl
of
top
is
signal
clk_ipb
,
rst_ipb
,
nuke
,
soft_rst
,
phy_rst_e
,
userled
:
std_logic
;
signal
mac_addr
:
std_logic_vector
(
47
downto
0
);
signal
ip_addr
:
std_logic_vector
(
31
downto
0
);
signal
ipb_out
:
ipb_wbus
;
signal
ipb_in
:
ipb_rbus
;
signal
inf_leds
:
std_logic_vector
(
1
downto
0
);
begin
-- Infrastructure
infra
:
entity
work
.
enclustra_ax3_pm3_infra
port
map
(
sysclk
=>
sysclk
,
clk_ipb_o
=>
clk_ipb
,
rst_ipb_o
=>
rst_ipb
,
rst125_o
=>
phy_rst_e
,
nuke
=>
nuke
,
soft_rst
=>
soft_rst
,
leds
=>
inf_leds
,
rgmii_txd
=>
rgmii_txd
,
rgmii_tx_ctl
=>
rgmii_tx_ctl
,
rgmii_txc
=>
rgmii_txc
,
rgmii_rxd
=>
rgmii_rxd
,
rgmii_rx_ctl
=>
rgmii_rx_ctl
,
rgmii_rxc
=>
rgmii_rxc
,
mac_addr
=>
mac_addr
,
ip_addr
=>
ip_addr
,
ipb_in
=>
ipb_in
,
ipb_out
=>
ipb_out
);
leds
<=
not
(
'0'
&
userled
&
inf_leds
);
phy_rstn
<=
not
phy_rst_e
;
mac_addr
<=
X"020ddba1151"
&
not
cfg
;
-- Careful here, arbitrary addresses do not always work
ip_addr
<=
X"c0a8c81"
&
not
cfg
;
-- 192.168.200.16+n
-- ipbus slaves live in the entity below, and can expose top-level ports
-- The ipbus fabric is instantiated within.
slaves
:
entity
work
.
ipbus_example
port
map
(
ipb_clk
=>
clk_ipb
,
ipb_rst
=>
rst_ipb
,
ipb_in
=>
ipb_out
,
ipb_out
=>
ipb_in
,
nuke
=>
nuke
,
soft_rst
=>
soft_rst
,
userled
=>
userled
);
end
rtl
;
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch
deleted
100644 → 0
View file @
98468998
--- /users/phdgc//DUNE/firmware/PDTS/work/build/src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl 2017-08-22 15:31:37.014565607 +0100
+++ ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl 2018-02-19 09:57:25.320449541 +0000
@@ -20,9 +20,11 @@
set_false_path -through [get_nets infra/clocks/nuke_i]
set_property IOSTANDARD LVCMOS25 [get_ports sysclk]
+#set_property IOSTANDARD LVCMOS33 [get_ports sysclk]
set_property PACKAGE_PIN P17 [get_ports sysclk]
set_property IOSTANDARD LVCMOS25 [get_ports {leds[*]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
set_property SLEW SLOW [get_ports {leds[*]}]
set_property PACKAGE_PIN M16 [get_ports {leds[0]}]
set_property PACKAGE_PIN M17 [get_ports {leds[1]}]
@@ -43,13 +45,15 @@
set_property PACKAGE_PIN V16 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN R16 [get_ports {rgmii_rx_ctl}]
set_property PACKAGE_PIN T14 [get_ports {rgmii_rxc}]
+
set_property PACKAGE_PIN M13 [get_ports {phy_rstn}]
false_path {phy_rstn} sysclk
-set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
-set_property PULLUP TRUE [get_ports {cfg[*]}]
-set_property PACKAGE_PIN K2 [get_ports {cfg[0]}]
-set_property PACKAGE_PIN K1 [get_ports {cfg[1]}]
-set_property PACKAGE_PIN J4 [get_ports {cfg[2]}]
-set_property PACKAGE_PIN H4 [get_ports {cfg[3]}]
+
+#set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
+#set_property PULLUP TRUE [get_ports {cfg[*]}]
+#set_property PACKAGE_PIN K2 [get_ports {cfg[0]}]
+#set_property PACKAGE_PIN K1 [get_ports {cfg[1]}]
+#set_property PACKAGE_PIN J4 [get_ports {cfg[2]}]
+#set_property PACKAGE_PIN H4 [get_ports {cfg[3]}]
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl.sav
deleted
100644 → 0
View file @
98468998
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
proc false_path {patt clk} {
set p [get_ports -quiet $patt -filter {direction != out}]
if {[llength $p] != 0} {
set_input_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != out}]
set_false_path -from [get_ports $patt -filter {direction != out}]
}
set p [get_ports -quiet $patt -filter {direction != in}]
if {[llength $p] != 0} {
set_output_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != in}]
set_false_path -to [get_ports $patt -filter {direction != in}]
}
}
# System clock (200MHz)
create_clock -period 20.000 -name sysclk [get_ports sysclk]
set_false_path -through [get_pins infra/clocks/rst_reg/Q]
set_false_path -through [get_nets infra/clocks/nuke_i]
set_property IOSTANDARD LVCMOS25 [get_ports sysclk]
set_property PACKAGE_PIN P17 [get_ports sysclk]
set_property IOSTANDARD LVCMOS25 [get_ports {leds[*]}]
set_property SLEW SLOW [get_ports {leds[*]}]
set_property PACKAGE_PIN M16 [get_ports {leds[0]}]
set_property PACKAGE_PIN M17 [get_ports {leds[1]}]
set_property PACKAGE_PIN L18 [get_ports {leds[2]}]
set_property PACKAGE_PIN M18 [get_ports {leds[3]}]
false_path {leds[*]} sysclk
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_* phy_rstn}]
set_property PACKAGE_PIN R18 [get_ports {rgmii_txd[0]}]
set_property PACKAGE_PIN T18 [get_ports {rgmii_txd[1]}]
set_property PACKAGE_PIN U17 [get_ports {rgmii_txd[2]}]
set_property PACKAGE_PIN U18 [get_ports {rgmii_txd[3]}]
set_property PACKAGE_PIN T16 [get_ports {rgmii_tx_ctl}]
set_property PACKAGE_PIN N16 [get_ports {rgmii_txc}]
set_property PACKAGE_PIN U16 [get_ports {rgmii_rxd[0]}]
set_property PACKAGE_PIN V17 [get_ports {rgmii_rxd[1]}]
set_property PACKAGE_PIN V15 [get_ports {rgmii_rxd[2]}]
set_property PACKAGE_PIN V16 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN R16 [get_ports {rgmii_rx_ctl}]
set_property PACKAGE_PIN T14 [get_ports {rgmii_rxc}]
set_property PACKAGE_PIN M13 [get_ports {phy_rstn}]
false_path {phy_rstn} sysclk
set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
set_property PULLUP TRUE [get_ports {cfg[*]}]
set_property PACKAGE_PIN K2 [get_ports {cfg[0]}]
set_property PACKAGE_PIN K1 [get_ports {cfg[1]}]
set_property PACKAGE_PIN J4 [get_ports {cfg[2]}]
set_property PACKAGE_PIN H4 [get_ports {cfg[3]}]
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl
deleted
100644 → 0
View file @
98468998
set_property FILE_TYPE
{
VHDL 2008
}
[
get_files DUTInterface_AIDA_rtl.vhd
]
set_property FILE_TYPE
{
VHDL 2008
}
[
get_files enclustra_ax3_pm3_infra.vhd
]
# ... or use this to set all files to VHDL 2008
# set_property file_type {VHDL 2008
}
[
get_files
[
get_filesets sources_1
]]
reorder_files -fileset constrs_1 -after
[
get_files enclustra_ax3_pm3.tcl
]
[
get_files TLU_enclustra_v1e.xdc
]
set_property PROCESSING_ORDER LATE
[
get_files TLU_enclustra_v1e.xdc
]
exit
AIDA_tlu/scripts/build_tlu_firmware.sh
View file @
678b4c67
...
...
@@ -4,19 +4,22 @@
IPBUS_BRANCH
=
"-b v1.6"
TLU_BRANCH
=
"-b 1e000024"
echo
"Creating working directory"
echo
"
BUILD:
Creating working directory"
[
-d
work
]
&&
echo
"Directory Exists"
||
mkdir
work
cd
work
IPBB_VERSION
=
"0.5.2"
echo
"Installing IPBB version
${
IPBB_VERSION
}
"
echo
"
BUILD:
Installing IPBB version
${
IPBB_VERSION
}
"
[
-d
ipbb-
${
IPBB_VERSION
}
]
&&
echo
"ipbb-
${
IPBB_VERSION
}
already installed"
||
curl
-L
https://github.com/ipbus/ipbb/archive/v
${
IPBB_VERSION
}
.tar.gz |
tar
xvz
# ( or git clone git@github.com:ipbus/ipbb.git )
source
ipbb-
${
IPBB_VERSION
}
/env.sh
echo
"BUILD: Initiaalizing build area"
ipbb init build
cd
build
echo
"BUILD: Checking out TLU code and IPBus code"
ipbb add git https://github.com/ipbus/ipbus-firmware.git
${
IPBUS_BRANCH
}
ipbb add git https://ohwr.org/project/fmc-mtlu-gw.git
${
TLU_BRANCH
}
# For read/write load a valid ssh key and use the repo below ....
...
...
@@ -33,16 +36,15 @@ ipbb vivado project
echo
"BUILD: creating IPBus address decoder"
ipbb vivado gendecoders
echo
"Copying generated decoder into source tree"
echo
"
BUILD:
Copying generated decoder into source tree"
cp
decoders/ipbus_decode_TLUaddrmap.vhd ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/hdl/ipbus_decode_TLUaddrmap.vhd
# Set TLU timing contraints *.xdc file to have "late" processing order
# vivado -mode tcl -nojournal -nolog -notrace -source ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl top/top.xpr
echo
"BUILD: ipbb impl"
ipbb vivado impl
echo
"BUILD: ipbb bitfile"
ipbb vivado bitfile
echo
"BUILD: ipbb package"
ipbb vivado package
echo
"BUILD: Finished. Deactivating ipbb"
deactivate
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