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AIDA-2020 TLU - Gateware
Commit 481f68b1 authored by David Cussans's avatar David Cussans
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Merge branch 'dcussans/ipbus1v6_update' into 'master' 

Dcussans/ipbus1v6 update

See merge request !1
parents 9eab5368 678b4c67
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AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_a35.dep deleted 100644 → 0
View file @ 9eab5368
@device_family = "artix7"
@device_name = "xc7a35t"
@device_package = "csg324"
@device_speed = "-2"
@boardname = "enclustra_ax3_pm3"
setup settings_v7.tcl
# src top_enclustra_ax3_pm3.vhd
include enclustra_ax3_pm3_infra.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
src --cd ../ucf enclustra_ax3_pm3.tcl
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/cfg/enclustra_ax3_pm3_infra.dep
View file @ 481f68b1
......@@ -23,12 +23,15 @@
#
#-------------------------------------------------------------------------------
src enclustra_ax3_pm3_infra.vhd
src -c ipbus-firmware:components/ipbus_util clocks_7s_extphy_se.vhd ipbus_clock_div.vhd led_stretcher.vhd
include -c ipbus-firmware:components/ipbus_core
src --vhdl2008 enclustra_ax3_pm3_infra.vhd
src -c ipbus-firmware:components/ipbus_util clocks/clocks_7s_extphy_se.vhd ipbus_clock_div.vhd led_stretcher.vhd
src -c ipbus-firmware:components/ipbus_util masters/ipbus_ctrl.vhd
include -c ipbus-firmware:components/ipbus_transport_udp
# include -c ipbus-firmware:components/ipbus_core
include -c ipbus-firmware:components/ipbus_eth artix_rgmii.dep
# Include simulated Ethernet - even though the Generate statement will ensure it never gets used.
src -c ipbus-firmware:components/ipbus_eth ../sim/eth_mac_sim.vhd
src -c ipbus-firmware:components/modelsim_fli/eth ../sim/eth_mac_sim.vhd
src -c ipbus-firmware:components/ipbus_core ipbus_fabric_sel.vhd ipbus_package.vhd
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/enclustra_ax3_pm3_infra-example.vhd deleted 100644 → 0
View file @ 9eab5368
-- enclustra_ax3_pm3_infra
--
-- Example "infra" file.
-- DO NOT USE THIS FILE.
-- Use the "patch" file to patch enclustra_ax3_pm3_infra.vhd in
-- ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl
-- David Cussans, January 2019
--
-- Original:
-- Dave Newbold, June 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.all;
entity enclustra_ax3_pm3_infra is
port(
sysclk: in std_logic; -- 50MHz board crystal clock
clk_ipb_o: out std_logic; -- IPbus clock
rst_ipb_o: out std_logic;
clk125_o: out std_logic;
rst125_o: out std_logic;
clk_aux_o: out std_logic; -- 50MHz clock
rst_aux_o: out std_logic;
nuke: in std_logic; -- The signal of doom
soft_rst: in std_logic; -- The signal of lesser doom
leds: out std_logic_vector(1 downto 0); -- status LEDs
rgmii_txd: out std_logic_vector(3 downto 0);
rgmii_tx_ctl: out std_logic;
rgmii_txc: out std_logic;
rgmii_rxd: in std_logic_vector(3 downto 0);
rgmii_rx_ctl: in std_logic;
rgmii_rxc: in std_logic;
mac_addr: in std_logic_vector(47 downto 0); -- MAC address
ip_addr: in std_logic_vector(31 downto 0); -- IP address
ipb_in: in ipb_rbus; -- ipbus
ipb_out: out ipb_wbus
);
end enclustra_ax3_pm3_infra;
architecture rtl of enclustra_ax3_pm3_infra is
signal clk125_fr, clk125, clk125_90, clk200, clk_ipb, clk_ipb_i, locked, rst125, rst_ipb, rst_ipb_ctrl, rst_eth, onehz, pkt: std_logic;
signal mac_tx_data, mac_rx_data: std_logic_vector(7 downto 0);
signal mac_tx_valid, mac_tx_last, mac_tx_error, mac_tx_ready, mac_rx_valid, mac_rx_last, mac_rx_error: std_logic;
signal led_p: std_logic_vector(0 downto 0);
begin
-- DCM clock generation for internal bus, ethernet
clocks: entity work.clocks_7s_extphy_se
port map(
sysclk => sysclk,
clko_125 => clk125,
clko_125_90 => clk125_90,
clko_200 => clk200,
clko_ipb => clk_ipb_i,
locked => locked,
nuke => nuke,
soft_rst => soft_rst,
rsto_125 => rst125,
rsto_ipb => rst_ipb,
rsto_ipb_ctrl => rst_ipb_ctrl,
onehz => onehz
);
clk_ipb <= clk_ipb_i; -- Best to align delta delays on all clocks for simulation
clk_ipb_o <= clk_ipb_i;
rst_ipb_o <= rst_ipb;
clk125_o <= clk125;
rst125_o <= rst125;
stretch: entity work.led_stretcher
generic map(
WIDTH => 1
)
port map(
clk => clk125,
d(0) => pkt,
q => led_p
);
leds <= (led_p(0), locked and onehz);
-- Ethernet MAC core and PHY interface
eth: entity work.eth_7s_rgmii
port map(
clk125 => clk125,
clk125_90 => clk125_90,
clk200 => clk200,
rst => rst125,
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
tx_data => mac_tx_data,
tx_valid => mac_tx_valid,
tx_last => mac_tx_last,
tx_error => mac_tx_error,
tx_ready => mac_tx_ready,
rx_data => mac_rx_data,
rx_valid => mac_rx_valid,
rx_last => mac_rx_last,
rx_error => mac_rx_error
);
-- ipbus control logic
ipbus: entity work.ipbus_ctrl
port map(
mac_clk => clk125,
rst_macclk => rst125,
ipb_clk => clk_ipb,
rst_ipb => rst_ipb_ctrl,
mac_rx_data => mac_rx_data,
mac_rx_valid => mac_rx_valid,
mac_rx_last => mac_rx_last,
mac_rx_error => mac_rx_error,
mac_tx_data => mac_tx_data,
mac_tx_valid => mac_tx_valid,
mac_tx_last => mac_tx_last,
mac_tx_error => mac_tx_error,
mac_tx_ready => mac_tx_ready,
ipb_out => ipb_out,
ipb_in => ipb_in,
mac_addr => mac_addr,
ip_addr => ip_addr,
pkt => pkt
);
end rtl;
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/hdl/top_enclustra_ax3_pm3.vhd deleted 100644 → 0
View file @ 9eab5368
-- Top-level design for ipbus demo
--
-- This version is for Enclustra AX3 module, using the RGMII PHY on the PM3 baseboard
--
-- You must edit this file to set the IP and MAC addresses
--
-- Dave Newbold, 4/10/16
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipbus.ALL;
entity top is port(
sysclk: in std_logic;
leds: out std_logic_vector(3 downto 0); -- status LEDs
cfg: in std_logic_vector(3 downto 0); -- switches
rgmii_txd: out std_logic_vector(3 downto 0);
rgmii_tx_ctl: out std_logic;
rgmii_txc: out std_logic;
rgmii_rxd: in std_logic_vector(3 downto 0);
rgmii_rx_ctl: in std_logic;
rgmii_rxc: in std_logic;
phy_rstn: out std_logic
);
end top;
architecture rtl of top is
signal clk_ipb, rst_ipb, nuke, soft_rst, phy_rst_e, userled: std_logic;
signal mac_addr: std_logic_vector(47 downto 0);
signal ip_addr: std_logic_vector(31 downto 0);
signal ipb_out: ipb_wbus;
signal ipb_in: ipb_rbus;
signal inf_leds: std_logic_vector(1 downto 0);
begin
-- Infrastructure
infra: entity work.enclustra_ax3_pm3_infra
port map(
sysclk => sysclk,
clk_ipb_o => clk_ipb,
rst_ipb_o => rst_ipb,
rst125_o => phy_rst_e,
nuke => nuke,
soft_rst => soft_rst,
leds => inf_leds,
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
mac_addr => mac_addr,
ip_addr => ip_addr,
ipb_in => ipb_in,
ipb_out => ipb_out
);
leds <= not ('0' & userled & inf_leds);
phy_rstn <= not phy_rst_e;
mac_addr <= X"020ddba1151" & not cfg; -- Careful here, arbitrary addresses do not always work
ip_addr <= X"c0a8c81" & not cfg; -- 192.168.200.16+n
-- ipbus slaves live in the entity below, and can expose top-level ports
-- The ipbus fabric is instantiated within.
slaves: entity work.ipbus_example
port map(
ipb_clk => clk_ipb,
ipb_rst => rst_ipb,
ipb_in => ipb_out,
ipb_out => ipb_in,
nuke => nuke,
soft_rst => soft_rst,
userled => userled
);
end rtl;
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.patch deleted 100644 → 0
View file @ 9eab5368
--- /users/phdgc//DUNE/firmware/PDTS/work/build/src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl 2017-08-22 15:31:37.014565607 +0100
+++ ../../src/ipbus-firmware/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl 2018-02-19 09:57:25.320449541 +0000
@@ -20,9 +20,11 @@
set_false_path -through [get_nets infra/clocks/nuke_i]
set_property IOSTANDARD LVCMOS25 [get_ports sysclk]
+#set_property IOSTANDARD LVCMOS33 [get_ports sysclk]
set_property PACKAGE_PIN P17 [get_ports sysclk]
set_property IOSTANDARD LVCMOS25 [get_ports {leds[*]}]
+#set_property IOSTANDARD LVCMOS33 [get_ports {leds[*]}]
set_property SLEW SLOW [get_ports {leds[*]}]
set_property PACKAGE_PIN M16 [get_ports {leds[0]}]
set_property PACKAGE_PIN M17 [get_ports {leds[1]}]
@@ -43,13 +45,15 @@
set_property PACKAGE_PIN V16 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN R16 [get_ports {rgmii_rx_ctl}]
set_property PACKAGE_PIN T14 [get_ports {rgmii_rxc}]
+
set_property PACKAGE_PIN M13 [get_ports {phy_rstn}]
false_path {phy_rstn} sysclk
-set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
-set_property PULLUP TRUE [get_ports {cfg[*]}]
-set_property PACKAGE_PIN K2 [get_ports {cfg[0]}]
-set_property PACKAGE_PIN K1 [get_ports {cfg[1]}]
-set_property PACKAGE_PIN J4 [get_ports {cfg[2]}]
-set_property PACKAGE_PIN H4 [get_ports {cfg[3]}]
+
+#set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
+#set_property PULLUP TRUE [get_ports {cfg[*]}]
+#set_property PACKAGE_PIN K2 [get_ports {cfg[0]}]
+#set_property PACKAGE_PIN K1 [get_ports {cfg[1]}]
+#set_property PACKAGE_PIN J4 [get_ports {cfg[2]}]
+#set_property PACKAGE_PIN H4 [get_ports {cfg[3]}]
AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth/firmware/ucf/enclustra_ax3_pm3.tcl.sav deleted 100644 → 0
View file @ 9eab5368
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
proc false_path {patt clk} {
set p [get_ports -quiet $patt -filter {direction != out}]
if {[llength $p] != 0} {
set_input_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != out}]
set_false_path -from [get_ports $patt -filter {direction != out}]
}
set p [get_ports -quiet $patt -filter {direction != in}]
if {[llength $p] != 0} {
set_output_delay 0 -clock [get_clocks $clk] [get_ports $patt -filter {direction != in}]
set_false_path -to [get_ports $patt -filter {direction != in}]
}
}
# System clock (200MHz)
create_clock -period 20.000 -name sysclk [get_ports sysclk]
set_false_path -through [get_pins infra/clocks/rst_reg/Q]
set_false_path -through [get_nets infra/clocks/nuke_i]
set_property IOSTANDARD LVCMOS25 [get_ports sysclk]
set_property PACKAGE_PIN P17 [get_ports sysclk]
set_property IOSTANDARD LVCMOS25 [get_ports {leds[*]}]
set_property SLEW SLOW [get_ports {leds[*]}]
set_property PACKAGE_PIN M16 [get_ports {leds[0]}]
set_property PACKAGE_PIN M17 [get_ports {leds[1]}]
set_property PACKAGE_PIN L18 [get_ports {leds[2]}]
set_property PACKAGE_PIN M18 [get_ports {leds[3]}]
false_path {leds[*]} sysclk
set_property IOSTANDARD LVCMOS25 [get_ports {rgmii_* phy_rstn}]
set_property PACKAGE_PIN R18 [get_ports {rgmii_txd[0]}]
set_property PACKAGE_PIN T18 [get_ports {rgmii_txd[1]}]
set_property PACKAGE_PIN U17 [get_ports {rgmii_txd[2]}]
set_property PACKAGE_PIN U18 [get_ports {rgmii_txd[3]}]
set_property PACKAGE_PIN T16 [get_ports {rgmii_tx_ctl}]
set_property PACKAGE_PIN N16 [get_ports {rgmii_txc}]
set_property PACKAGE_PIN U16 [get_ports {rgmii_rxd[0]}]
set_property PACKAGE_PIN V17 [get_ports {rgmii_rxd[1]}]
set_property PACKAGE_PIN V15 [get_ports {rgmii_rxd[2]}]
set_property PACKAGE_PIN V16 [get_ports {rgmii_rxd[3]}]
set_property PACKAGE_PIN R16 [get_ports {rgmii_rx_ctl}]
set_property PACKAGE_PIN T14 [get_ports {rgmii_rxc}]
set_property PACKAGE_PIN M13 [get_ports {phy_rstn}]
false_path {phy_rstn} sysclk
set_property IOSTANDARD LVCMOS25 [get_ports {cfg[*]}]
set_property PULLUP TRUE [get_ports {cfg[*]}]
set_property PACKAGE_PIN K2 [get_ports {cfg[0]}]
set_property PACKAGE_PIN K1 [get_ports {cfg[1]}]
set_property PACKAGE_PIN J4 [get_ports {cfg[2]}]
set_property PACKAGE_PIN H4 [get_ports {cfg[3]}]
AIDA_tlu/projects/TLU_v1e/firmware/cfg/enclustra_ax3_pm3_a35.dep
View file @ 481f68b1
......@@ -5,15 +5,21 @@
@boardname = "enclustra_ax3_pm3"
setup settings_v7.tcl
# Top level file
src top_enclustra_tlu_v1e.vhd
#
include -c AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_infra.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
src -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth --cd ../ucf enclustra_ax3_pm3.tcl
#
src top_enclustra_tlu_v1e.vhd
src --cd ../ucf TLU_enclustra_v1e.tcl
#setup -f --cd ../ucf TLU_enclustra_v1e.xdc
src -c ipbus-firmware:boards/enclustra_ax3_pm3/synth --cd ../ucf enclustra_ax3_pm3.tcl
# src --cd ../ucf enclustra_ax3_pm3.tcl
src --cd ../ucf I2C_constr.xdc
src --cd ../ucf TLU_enclustra_v1e.xdc
#include -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_a35.dep
AIDA_tlu/projects/TLU_v1e/firmware/cfg/settings_v7.tcl
View file @ 481f68b1
set obj [get_projects top]
set obj [get_projects TLU_1e]
set_property "default_lib" "xil_defaultlib" $obj
set_property "simulator_language" "Mixed" $obj
set_property "source_mgmt_mode" "DisplayOnly" $obj
......
AIDA_tlu/projects/TLU_v1e/firmware/hdl/top_enclustra_tlu_v1e.vhd
View file @ 481f68b1
......@@ -63,7 +63,7 @@ entity top is
);
port(
--Clock
sysclk: in std_logic; --50 MHz clock input from FPGA
osc_clk: in std_logic; --50 MHz clock input from FPGA
--clk_enclustra: in std_logic; --Enclustra onboard oscillator 50 MHz. Used for the IPBus block
sysclk_50_o_p : out std_logic; --50 MHz clock output to FMC pins
sysclk_50_o_n : out std_logic; --50 MHz clock output to FMC pins
......@@ -786,7 +786,7 @@ begin
IBUFG_inst: IBUFG
port map (
O => clk_encl_buf,
I => sysclk -- clk_enclustra
I => osc_clk -- clk_enclustra
);
------------------------------------------
......
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc → AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.tcl
View file @ 481f68b1
......@@ -138,7 +138,7 @@ create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_po
##set_clock_groups -asynchronous -group [list [get_clocks clk_ipb_i] [get_clocks sysclk]] -group [list [get_clocks s_clk160] [get_clocks sysclk_40_i_p]]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks sysclk] -group [get_clocks -include_generated_clocks sysclk_40_i_p]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks osc_clk] -group [get_clocks -include_generated_clocks sysclk_40_i_p]
#set_input_delay -clock [get_clocks s_clk320]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
#set_input_delay -clock [get_clocks s_clk320]]] -rise -max 1.400 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
......@@ -180,10 +180,10 @@ set_input_delay -clock [get_clocks s_clk160] -max 3.300 [get_ports {busy_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -min 3.200 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -max 3.300 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15.000 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17.000 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks ipbus_clk] -min 15.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks ipbus_clk] -max 17.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks ipbus_clk] -min 15.000 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks ipbus_clk] -max 17.000 [get_ports i2c_sda_b]
#
#set_output_delay -clock [get_clocks clk_ipb_i] -min 1 [get_ports i2c_scl_b]
#set_output_delay -clock [get_clocks clk_ipb_i] -max 30 [get_ports i2c_scl_b]
......
AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl deleted 100644 → 0
View file @ 9eab5368
set_property FILE_TYPE {VHDL 2008} [get_files DUTInterface_AIDA_rtl.vhd]
set_property FILE_TYPE {VHDL 2008} [get_files enclustra_ax3_pm3_infra.vhd]
# ... or use this to set all files to VHDL 2008
# set_property file_type {VHDL 2008} [get_files [get_filesets sources_1]]
reorder_files -fileset constrs_1 -after [get_files enclustra_ax3_pm3.tcl] [get_files TLU_enclustra_v1e.xdc]
set_property PROCESSING_ORDER LATE [get_files TLU_enclustra_v1e.xdc]
exit
AIDA_tlu/projects/sim/firmware/cfg/top_sim.dep
View file @ 481f68b1
......@@ -35,9 +35,9 @@ src -c AIDA_tlu/projects/TLU_v1e top_enclustra_tlu_v1e.vhd
src -c AIDA_tlu/projects/sim --vhdl2008 infra_sim.vhd
src -c ipbus-firmware:components/ipbus_util clocks_7s_extphy_se.vhd led_stretcher.vhd ipbus_clock_div.vhd
src -c ipbus-firmware:components/ipbus_util clocks/clocks_7s_extphy_se.vhd led_stretcher.vhd ipbus_clock_div.vhd
src -c ipbus-firmware:components/ipbus_eth ../sim/eth_mac_sim.vhd
src -c ipbus-firmware:components/modelsim_fli/eth ../sim/eth_mac_sim.vhd
#
include -c AIDA_tlu/projects/TLU_v1e tlu_1e.dep
......
AIDA_tlu/scripts/build_tlu_firmware.sh
View file @ 481f68b1
#!/bin/sh
# Put which branch of Git to use here...
IPBUS_BRANCH="-b v1.3"
IPBUS_BRANCH="-b v1.6"
TLU_BRANCH="-b 1e000024"
mkdir work
echo "BUILD: Creating working directory"
[ -d work ] && echo "Directory Exists" || mkdir work
cd work
# IPBB_VERSION="0.3.13"
IPBB_VERSION="0.4.3"
curl -L https://github.com/ipbus/ipbb/archive/v${IPBB_VERSION}.tar.gz | tar xvz
IPBB_VERSION="0.5.2"
echo "BUILD: Installing IPBB version ${IPBB_VERSION}"
[ -d ipbb-${IPBB_VERSION} ] && echo "ipbb-${IPBB_VERSION} already installed" || curl -L https://github.com/ipbus/ipbb/archive/v${IPBB_VERSION}.tar.gz | tar xvz
# ( or git clone git@github.com:ipbus/ipbb.git )
source ipbb-${IPBB_VERSION}/env.sh
echo "BUILD: Initiaalizing build area"
ipbb init build
cd build
echo "BUILD: Checking out TLU code and IPBus code"
ipbb add git https://github.com/ipbus/ipbus-firmware.git ${IPBUS_BRANCH}
ipbb add git https://ohwr.org/project/fmc-mtlu-gw.git ${TLU_BRANCH}
# For read/write load a valid ssh key and use the repo below ....
# ipbb add git ssh://git@ohwr.org/fmc-projects/fmc-mtlu/fmc-mtlu-gw.git
# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
echo "Generating address table VHDL from XML file"
pushd src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/addr_table
pwd
/opt/cactus/bin/uhal/tools/gen_ipbus_addr_decode -v TLUaddrmap.xml
#copy resulting file ( ipbus_decode_TLUaddrmap.vhd ) to work/build/src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/hdl/
mv ipbus_decode_TLUaddrmap.vhd ../firmware/hdl/
popd
echo "BUILD: ipbb proj create"
ipbb proj create vivado TLU_1e fmc-mtlu-gw:AIDA_tlu/projects/TLU_v1e -t top_tlu_1e_a35.dep
cd proj/TLU_1e
echo "BUILD: creating VIVADO project"
ipbb vivado project
# Set TLU timing contraints *.xdc file to have "late" processing order
vivado -mode tcl -nojournal -nolog -notrace -source ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl top/top.xpr
echo "BUILD: creating IPBus address decoder"
ipbb vivado gendecoders
echo "BUILD: Copying generated decoder into source tree"
cp decoders/ipbus_decode_TLUaddrmap.vhd ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/hdl/ipbus_decode_TLUaddrmap.vhd
echo "BUILD: ipbb impl"
ipbb vivado impl
......@@ -46,4 +45,6 @@ echo "BUILD: ipbb bitfile"
ipbb vivado bitfile
echo "BUILD: ipbb package"
ipbb vivado package
echo "BUILD: Finished. Deactivating ipbb"
deactivate
AIDA_tlu/scripts/simulate_tlu_firmware.sh
View file @ 481f68b1
#!/bin/sh
# Put which branch of Git to use here...
IPBUS_BRANCH="-b v1.3"
TLU_BRANCH="-b 1e000022"
IPBUS_BRANCH="-b v1.6"
TLU_BRANCH="-b 1e000024"
mkdir work
echo "Creating working directory"
[ -d work ] && echo "Directory Exists" || mkdir work
cd work
# IPBB_VERSION="0.3.13"
IPBB_VERSION="0.4.3"
curl -L https://github.com/ipbus/ipbb/archive/v${IPBB_VERSION}.tar.gz | tar xvz
IPBB_VERSION="0.5.2"
echo "Installing IPBB version ${IPBB_VERSION}"
[ -d ipbb-${IPBB_VERSION} ] && echo "ipbb-${IPBB_VERSION} already installed" || curl -L https://github.com/ipbus/ipbb/archive/v${IPBB_VERSION}.tar.gz | tar xvz
# ( or git clone git@github.com:ipbus/ipbb.git )
source ipbb-${IPBB_VERSION}/env.sh
......@@ -22,18 +25,18 @@ ipbb add git https://ohwr.org/project/fmc-mtlu-gw.git ${TLU_BRANCH}
# ipbb add git ssh://git@ohwr.org/fmc-projects/fmc-mtlu/fmc-mtlu-gw.git
# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
echo "Generating address table VHDL from XML file"
pushd src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/addr_table
pwd
/opt/cactus/bin/uhal/tools/gen_ipbus_addr_decode -v TLUaddrmap.xml
#copy resulting file ( ipbus_decode_TLUaddrmap.vhd ) to work/build/src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/hdl/
mv ipbus_decode_TLUaddrmap.vhd ../firmware/hdl/
popd
echo "Creating project"
ipbb proj create sim TLU_1e_sim fmc-mtlu-gw:AIDA_tlu/projects/sim -t top_sim.dep
source /software/CAD/setup_mentor2019.sh
cd proj/TLU_1e_sim
# source /software/CAD/setup_mentor2019.sh
echo "Generating address table VHDL from XML file"
ipbb sim gendecoders
ipbb sim setup-simlib ipcores fli
......
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