@@ -27,71 +27,7 @@ It is always possible to compile the firmware to obtain the *.bit and *.mcs file
### Building Firmware
The master firmware uses the [ipbb](https://github.com/ipbus/ipbb) build tool, and requires the ipbus system firmware.
The master firmware uses the [ipbb](https://github.com/ipbus/ipbb) build tool, and requires the ipbus system firmware together with the Xilinx Vivado software.
Set up the environment for Xilinx Vivado, then:
There is a script availble which execute the commands necessary to produce an FPGA configuration file (*.bit file). Instructions are available at https://ohwr.org/project/fmc-mtlu-gw/wikis/Building-AIDA-2020-TLU-firmware
```
# Put which branch of Git to use here...
IPBUS_BRANCH="-b v1.3"
TLU_BRANCH=""
mkdir work
cd work
IPBB_VERSION="0.3.13"
curl -L https://github.com/ipbus/ipbb/archive/v${IPBB_VERSION}.tar.gz | tar xvz
# In order to generate the VHDL to decode the addresses follow the instructions at https://ipbus.web.cern.ch/ipbus/doc/user/html/firmware/hwDevInstructions.html
echo "Generating address table VHDL from XML file"
