Commit a74e93c1 authored by David Cussans's avatar David Cussans

More tidying up of TLU firmware.

Should now build against IPBus v1.6
parent b1027c62
......@@ -12,12 +12,14 @@ src top_enclustra_tlu_v1e.vhd
include -c AIDA_tlu/boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_infra.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
src -c ipbus-firmware:boards/enclustra_ax3_pm3/synth --cd ../ucf enclustra_ax3_pm3.tcl
src --cd ../ucf TLU_enclustra_v1e.tcl
#setup -f --cd ../ucf TLU_enclustra_v1e.xdc
src -c ipbus-firmware:boards/enclustra_ax3_pm3/synth --cd ../ucf enclustra_ax3_pm3.tcl
# src --cd ../ucf enclustra_ax3_pm3.tcl
src --cd ../ucf I2C_constr.xdc
src --cd ../ucf TLU_enclustra_v1e.xdc
#include -c ipbus-firmware:boards/enclustra_ax3_pm3/base_fw/synth enclustra_ax3_pm3_a35.dep
......@@ -63,7 +63,7 @@ entity top is
sysclk: in std_logic; --50 MHz clock input from FPGA
osc_clk: in std_logic; --50 MHz clock input from FPGA
--clk_enclustra: in std_logic; --Enclustra onboard oscillator 50 MHz. Used for the IPBus block
sysclk_50_o_p : out std_logic; --50 MHz clock output to FMC pins
sysclk_50_o_n : out std_logic; --50 MHz clock output to FMC pins
......@@ -786,7 +786,7 @@ begin
port map (
O => clk_encl_buf,
I => sysclk -- clk_enclustra
I => osc_clk -- clk_enclustra
......@@ -138,7 +138,7 @@ create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_po
##set_clock_groups -asynchronous -group [list [get_clocks clk_ipb_i] [get_clocks sysclk]] -group [list [get_clocks s_clk160] [get_clocks sysclk_40_i_p]]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks sysclk] -group [get_clocks -include_generated_clocks sysclk_40_i_p]
set_clock_groups -asynchronous -group [get_clocks -include_generated_clocks osc_clk] -group [get_clocks -include_generated_clocks sysclk_40_i_p]
#set_input_delay -clock [get_clocks s_clk320]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
#set_input_delay -clock [get_clocks s_clk320]]] -rise -max 1.400 [get_ports -regexp -filter { NAME =~ ".*thresh.*" && DIRECTION == "IN" }]
......@@ -180,10 +180,10 @@ set_input_delay -clock [get_clocks s_clk160] -max 3.300 [get_ports {busy_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -min 3.200 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks s_clk160] -max 3.300 [get_ports {dut_clk_i[*]}]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks clk_ipb_i] -min 15.000 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks clk_ipb_i] -max 17.000 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks ipbus_clk] -min 15.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks ipbus_clk] -max 17.000 [get_ports i2c_scl_b]
set_input_delay -clock [get_clocks ipbus_clk] -min 15.000 [get_ports i2c_sda_b]
set_input_delay -clock [get_clocks ipbus_clk] -max 17.000 [get_ports i2c_sda_b]
#set_output_delay -clock [get_clocks clk_ipb_i] -min 1 [get_ports i2c_scl_b]
#set_output_delay -clock [get_clocks clk_ipb_i] -max 30 [get_ports i2c_scl_b]
......@@ -35,8 +35,9 @@ ipbb sim gendecoders
cp decoders/ipbus_decode_TLUaddrmap.vhd ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/hdl/ipbus_decode_TLUaddrmap.vhd
# Not needed if we rename *.xdc to *.tcl ...
# Set TLU timing contraints *.xdc file to have "late" processing order
vivado -mode tcl -nojournal -nolog -notrace -source ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl top/top.xpr
#vivado -mode tcl -nojournal -nolog -notrace -source ../../src/fmc-mtlu-gw/AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e_setProcessingOrder.tcl TLU_1e/TLU_1e.xpr
echo "BUILD: ipbb impl"
ipbb vivado impl
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