Previous commit contained serious error, as accidentally modified blo-input nets. It is corrected now + right nets assigned for PCB versioning

Testbench for burst mode testing updated. The overall gateware testbench also updated to show burst mode operation for short pulses

Added tcl script used in release 3 of the gateware. Should work for future releases, but care must be taken to modify the file list

Adds updated project with settings from tcl scrip also added. Top module modified to have correct LED output

The following sections were updated:
- 3.1 TTL input logic -- added reflection of no signal detect state in LSR
- 3.2 First pulse inhibit -- added delay before enabling the line to conv-common-gw
- 3.3 Line input logic -- added reflection of no signal detect state in LSR
- 3.4 Switches -- made figure more compact

Also updated ISE project file to test that nothing went wrong when these
modules were deleted.