Commit 7ab4f2b9 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

commiting everythin, but will require cleaning up

parent 0d465aee
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for CONV-BURST_CTRL design
--==============================================================================
--
-- author: Denia Bouhired (denia.bouhired@cern.ch)
--
-- date of creation: 20-09-2016
--
-- version: 1.0
--
-- description:
-- Simulation testbench for the new burst mode module to run in as part of the
-- CONV-TTL-BLO common gateware.
--
--
-- dependencies:
-- None.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 20-09-2016 Denia Bouhired File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
--use work.gencores_pkg.all;
--use work.wishbone_pkg.all;
-- use work.conv_common_gw_pkg.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
-- Clock periods
constant c_clk_20_per : time := 50 ns;
constant random_intervals : boolean := false;
component conv_burst_ctrl is
generic
(
g_pwidth : natural range 1 to 10 := 5;
g_duty_cycle_div : natural := 200;
g_max_burst_len : natural := 1000;
g_burst_timeout : natural := 60000
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_burst_i : in std_logic;
pulse_burst_o : out std_logic;
burst_err_p_o : out std_logic
);
end component conv_burst_ctrl;
component conv_dyn_burst_ctrl is
generic
(
g_pwidth : natural range 2 to 40 := 5;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 18;
g_1_pulse_energ :in integer := 10;
g_max_temp_rise :in integer range 0 to 1000000 := 1000
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
pulse_burst_i : in std_logic;
temp_rise_c : out integer;
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o : out std_logic
);
end component conv_dyn_burst_ctrl;
-- Signal declarations
signal clk_20 : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal burst_train : std_logic;
--signal burst_train_dyn : std_logic;
signal burst_train_regulated : std_logic;
signal burst_train_regulated_dyn : std_logic;
signal temp_rise_counter : integer;
signal rand_num : integer := 0;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- ============================================================================
--Instantiate the DUT: Burst controller averaged over 1000 pulses
--============================================================================
cmp_dut_1 : conv_burst_ctrl
generic map
(
g_pwidth => 5,
g_duty_cycle_div => 100,
g_max_burst_len => 3,
g_burst_timeout => 50000
)
port map(
clk_i => clk_20,
rst_n_i => rst,
en_i => en,
pulse_burst_i => burst_train,
pulse_burst_o => burst_train_regulated,
burst_err_p_o => open
);
-- burst_train_dyn <= burst_train;
--============================================================================
-- Instantiate the DUT: Dynamic
--============================================================================
cmp_dut_2 : conv_dyn_burst_ctrl
generic map
(
g_pwidth => 5,
g_duty_cycle_div => 100,
g_1_pulse_energ => 100,
g_max_temp_rise => 10000
)
port map(
clk_i => clk_20,
rst_n_i => rst,
en_i => en,
pulse_burst_i => burst_train,
pulse_burst_o => burst_train_regulated_dyn,
temp_rise_c => temp_rise_counter,
burst_err_p_o => open
);
--============================================================================
-- Generate clock signals
--============================================================================
p_clk_20 : process
begin
clk_20 <= '0';
wait for c_clk_20_per/2;
clk_20 <= '1';
wait for c_clk_20_per/2;
end process p_clk_20;
--============================================================================
-- Random number generator
--============================================================================
p_ran_gen : process
variable seed1, seed2: positive := 1; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 10000.0; -- the range of random values created will be 0 to +1000.
begin
uniform(seed1, seed2, rand); -- generate random number
rand_num <= integer(rand*range_of_rand); -- rescale to 0..1000, convert integer part
wait for 1000 ns;
end process p_ran_gen;
process
begin
rst <= '1';
wait for 2500 ns;
rst <= '0';
wait for 2000 ns;
rst <= '1';
wait;
end process;
process
begin
en <= '0';
wait for 5000 ns;
en <= '1';
wait;
end process;
--============================================================================
-- Pulse stimuli
--============================================================================
p_stim_burst : process
variable interval : time;-- := 1000 ns;
begin
while true loop
if random_intervals then
interval := rand_num * 1 ns;
else
interval := 250 ns;
end if;
burst_train <= '0';
wait for interval;
burst_train <= '1';
wait for 250 ns;
burst_train <= '0';
end loop;
end process p_stim_burst;
-- p_write_output : process (temp_rise_counter)
-- file F : text open write_mode is "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\sim\Release\temp_rise_counter.txt";
-- variable L : line;
-- begin
-- write (L, NOW, left, 10);
-- write (L, temp_rise_counter, left, 6);
-- writeline (F, L);
-- end process p_write_output;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
\ No newline at end of file
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--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for CONV-BURST_CTRL design
--==============================================================================
--
-- author: Denia Bouhired (denia.bouhired@cern.ch)
--
-- date of creation: 20-09-2016
--
-- version: 1.0
--
-- description:
-- Simulation testbench for the new burst mode module to run in as part of the
-- CONV-TTL-BLO common gateware.
--
--
-- dependencies:
-- None.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 20-09-2016 Denia Bouhired File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
--use work.gencores_pkg.all;
--use work.wishbone_pkg.all;
-- use work.conv_common_gw_pkg.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
-- Clock periods
constant c_clk_20_per : time := 50 ns;
constant random_intervals : boolean := false;
component conv_burst_ctrl is
generic
(
g_pwidth : natural range 1 to 10 := 5;
g_duty_cycle_div : natural := 200;
g_max_burst_len : natural := 1000;
g_burst_timeout : natural := 60000
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_burst_i : in std_logic;
pulse_burst_o : out std_logic;
burst_err_p_o : out std_logic
);
end component conv_burst_ctrl;
component conv_dyn_burst_ctrl is
generic
(
g_pwidth : natural range 2 to 40 := 5;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div : natural := 18;
g_1_pulse_energ :in integer := 10;
g_max_temp_rise :in integer := 1000
);
port
(
-- Clock and active-low reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Enable input, pulse generation is enabled when '1'
en_i : in std_logic;
pulse_burst_i : in std_logic;
temp_rise_c : out integer;
pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives
-- within a burst rejection phase
burst_err_p_o : out std_logic
);
end component conv_dyn_burst_ctrl;
-- Signal declarations
signal clk_20 : std_logic;
signal rst : std_logic;
signal en : std_logic;
signal burst_train : std_logic;
--signal burst_train_dyn : std_logic;
signal burst_train_regulated : std_logic;
signal burst_train_regulated_dyn : std_logic;
signal temp_rise_counter : integer;
signal rand_num : integer := 0;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- ============================================================================
--Instantiate the DUT: Burst controller averaged over 1000 pulses
--============================================================================
-- cmp_dut_1 : conv_burst_ctrl
-- generic map
-- (
-- g_pwidth => 5,
-- g_duty_cycle_div => 100,
-- g_max_burst_len => 3,
-- g_burst_timeout => 50000
-- )
-- port map(
-- clk_i => clk_20,
-- rst_n_i => not rst,
-- en_i => en,
-- pulse_burst_i => burst_train,
-- pulse_burst_o => burst_train_regulated,
-- burst_err_p_o => open
-- );
-- burst_train_dyn <= burst_train;
--============================================================================
-- Instantiate the DUT: Dynamic
--============================================================================
cmp_dut_2 : conv_dyn_burst_ctrl
generic map
(
g_pwidth => 5,
g_duty_cycle_div => 20,
g_1_pulse_energ => 20,
g_max_temp_rise => 60
)
port map(
clk_i => clk_20,
rst_n_i => not rst,
en_i => en,
pulse_burst_i => burst_train,
pulse_burst_o => burst_train_regulated,
temp_rise_c => temp_rise_counter,
burst_err_p_o => open
);
--============================================================================
-- Generate clock signals
--============================================================================
p_clk_20 : process
begin
clk_20 <= '0';
wait for c_clk_20_per/2;
clk_20 <= '1';
wait for c_clk_20_per/2;
end process p_clk_20;
--============================================================================
-- Random number generator
--============================================================================
p_ran_gen : process
variable seed1, seed2: positive := 1; -- seed values for random generator
variable rand: real; -- random real-number value in range 0 to 1.0
variable range_of_rand : real := 10000.0; -- the range of random values created will be 0 to +1000.
begin
uniform(seed1, seed2, rand); -- generate random number
rand_num <= integer(rand*range_of_rand); -- rescale to 0..1000, convert integer part
wait for 1000 ns;
end process p_ran_gen;
process
begin
rst <= '0';
wait for 2500 ns;
rst <= '1';
wait for 2000 ns;
rst <= '0';
wait;
end process;
process
begin
en <= '0';
wait for 1500 ns;
en <= '1';
wait;
end process;
--============================================================================
-- Pulse stimuli
--============================================================================
p_stim_burst : process
variable interval : time;-- := 1000 ns;
begin
while true loop
if random_intervals then
interval := rand_num * 1 ns;
else
interval := 500 ns;
end if;
burst_train <= '0';
wait for interval;
burst_train <= '1';
wait for 250 ns;
burst_train <= '0';
end loop;
end process p_stim_burst;
p_write_output : process (temp_rise_counter)
file F : text open write_mode is "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\sim\Release\temp_rise_counter.txt";
variable L : line;
begin
write (L, NOW, left, 10);
write (L, temp_rise_counter, left, 6);
writeline (F, L);
end process p_write_output;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
\ No newline at end of file
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Model Technology ModelSim SE-64 vlog 10.1c Compiler 2012.07 Jul 27 2012
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<?xml version="1.0" encoding="UTF-8"?>
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<messages>
</messages>
#*****************************************************************
# C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\compxlib.exe configuration file - compxlib.cfg
# Tue Sep 06 17:17:54 2016
#
# Important :-
# All options/variables must start from first column
#
#*****************************************************************
#
RELEASE_VERSION:14.7
#
RELEASE_BUILD:P.20131013
#
# set current simulator name
SIMULATOR_NAME:mti_se
#
# set current language name
LANGUAGE_NAME:all
#
# set compilation execution mode
EXECUTE:on
#
# print compilation command template in log file
LOG_CMD_TEMPLATE:off
#
# Hierarchical Output Directories
HIER_OUT_DIR:off
#
# print Pre-Compiled library info
PRECOMPILED_INFO:on
#
# create backup copy of setup files
BACKUP_SETUP_FILES:on
#
# use enhanced compilation techniques for faster library compilation
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FAST_COMPILE:on
#
# save compilation results to log file with the name specified with -log option
ADD_COMPILATION_RESULTS_TO_LOG:on
#
# abort compilation process if errors are detected in the library
ABORT_ON_ERROR:off
#
# compile library in the directory specified by the environment variable if the
# -dir option is not specified
OUTPUT_DIR_ENV:
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: ModelSim SE
SET:mti_se:MODELSIM=modelsim.ini
#
# ModelSim SE options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:mti_se:vhdl:u:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:s:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:c:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:r:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:i:-source -93 -novopt -explicit
OPTION:mti_se:vhdl:e:-93 -novopt -quiet -explicit
#
# ModelSim SE options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:mti_se:verilog:u:-source -novopt
OPTION:mti_se:verilog:s:-source -novopt
OPTION:mti_se:verilog:n:-source -novopt
OPTION:mti_se:verilog:c:-source -novopt
OPTION:mti_se:verilog:r:-source -novopt
OPTION:mti_se:verilog:i:-source -novopt
OPTION:mti_se:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: ModelSim PE
SET:mti_pe:MODELSIM=modelsim.ini
#
# ModelSim PE options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:mti_pe:vhdl:u:-source -93 -explicit
OPTION:mti_pe:vhdl:s:-source -93 -explicit
OPTION:mti_pe:vhdl:c:-source -93 -explicit
OPTION:mti_pe:vhdl:r:-source -93 -explicit
OPTION:mti_pe:vhdl:i:-source -93 -explicit
OPTION:mti_pe:vhdl:e:-93 -novopt -quiet -explicit
#
# ModelSim PE options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:mti_pe:verilog:u:-source
OPTION:mti_pe:verilog:s:-source
OPTION:mti_pe:verilog:n:-source
OPTION:mti_pe:verilog:c:-source
OPTION:mti_pe:verilog:r:-source
OPTION:mti_pe:verilog:i:-source
OPTION:mti_pe:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
# Setup file name: ModelSim DE
SET:mti_de:MODELSIM=modelsim.ini
#
# ModelSim DE options for VHDL Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:mti_de:vhdl:u:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:s:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:c:-source -93 -novopt -explicit
OPTION:mti_de:vhdl:r:-source -93 -novopt -explicit
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#
# ModelSim DE options for VERILOG Libraries
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# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:mti_de:verilog:u:-source -novopt
OPTION:mti_de:verilog:s:-source -novopt
OPTION:mti_de:verilog:n:-source -novopt
OPTION:mti_de:verilog:c:-source -novopt
OPTION:mti_de:verilog:r:-source -novopt
OPTION:mti_de:verilog:i:-source -novopt
OPTION:mti_de:verilog:e:-novopt -quiet
#
#///////////////////////////////////////////////////////////////////////
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SET:questasim:MODELSIM=modelsim.ini
#
# QuestaSim options for VHDL Libraries
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# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
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OPTION:questasim:vhdl:u:-source -93 -novopt -explicit
OPTION:questasim:vhdl:s:-source -93 -novopt -explicit
OPTION:questasim:vhdl:c:-source -93 -novopt -explicit
OPTION:questasim:vhdl:r:-source -93 -novopt -explicit
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#
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# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:questasim:verilog:u:-source -novopt
OPTION:questasim:verilog:s:-source -novopt
OPTION:questasim:verilog:n:-source -novopt
OPTION:questasim:verilog:c:-source -novopt
OPTION:questasim:verilog:r:-source -novopt
OPTION:questasim:verilog:i:-source -novopt
OPTION:questasim:verilog:e:-novopt -quiet
#
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# r (coolrunner) i (secureip) e (edk)
# vcom -work <library> <OPTION> <file_name>
#
OPTION:riviera:vhdl:u:-93
OPTION:riviera:vhdl:s:-93
OPTION:riviera:vhdl:c:-93
OPTION:riviera:vhdl:r:-93
OPTION:riviera:vhdl:i:-93
OPTION:riviera:vhdl:e:-93
#
# Aldec options for VERILOG Libraries
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# vlog -work <library> <OPTION> <file_name>
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OPTION:riviera:verilog:u:-v2k5
OPTION:riviera:verilog:s:-v2k5
OPTION:riviera:verilog:n:-v2k5
OPTION:riviera:verilog:c:-v2k5
OPTION:riviera:verilog:r:-v2k5
OPTION:riviera:verilog:i:-v2k5
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OPTION:active_hdl:vhdl:u:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:s:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:c:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:r:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:i:-93 -quiet -nowarn ELAB1_0026
OPTION:active_hdl:vhdl:e:-93 -quiet -nowarn ELAB1_0026
#
# Aldec options for VERILOG Libraries
# Syntax:-
# OPTION:<simulator_name>:<language>:<library>:<options>
# <library> :- u (unisim) s (simprim) c (xilinxcorelib)
# r (coolrunner) i (secureip) e (edk)
# vlog -work <library> <OPTION> <file_name>
#
OPTION:active_hdl:verilog:u:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:s:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:n:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:c:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:r:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:i:-v2k5 -quiet -msg 0
OPTION:active_hdl:verilog:e:-v2k5 -quiet -msg 0
#///////////////////////////////////////////////////////////////////////
# End
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\genrams\genram_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\wishbone\wishbone_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\top\conv_common_gw_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\common\gencores_pkg.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\ip_cores\general-cores\modules\common\gc_sync_ffs.vhd"
vhdl work "\\cern.ch\dfs\Users\d\debouhir\Documents\Projects\CONV-TTL-BlO\repo\conv-ttl-blo-gw\ip_cores\conv-common-gw\modules\conv_burst_ctrl.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_register.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd"
verilog work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_i2c_slave.vhd"
vhdl work "../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_ring_buf.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_reset_gen.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_regs.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_pulse_timetag.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_pulse_gen.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_man_trig.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/xwb_xil_multiboot.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd"
vhdl work "../../ip_cores/conv-common-gw/top/conv_common_gw.vhd"
verilog work "C:/Xilinx/14.7/ISE_DS/ISE//verilog/src/glbl.v"
######################################################################
##
## Filename: conv_dyn_burst_ctrl.udo
## Created on: Mon Oct 17 17:16:31 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation.
##
######################################################################
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/top/conv_common_gw_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vhdl work "../../ip_cores/conv-common-gw/modules/conv_dyn_burst_ctrl.vhd"
######################################################################
##
## Filename: conv_dyn_burst_ctrl_wave.fdo
## Created on: Mon Oct 17 17:16:32 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation windows.
##
######################################################################
add wave *
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="conv_ttl_blo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>conv_ttl_blo Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>conv_ttl_blo.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>conv_ttl_blo</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc7vx330t-3ffg1157</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 10/19/2016 - 15:21:53</center>
</BODY></HTML>
\ No newline at end of file
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
-intstyle "ise" -incremental -rangecheck -lib "secureip" -o "C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/syn/Release/testbench_isim_beh.exe" -prj "C:/Users/debouhir/work/CONV-TTL-BLO/repo/conv-ttl-blo-gw/syn/Release/testbench_beh.prj" "work.testbench"
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######################################################################
##
## Filename: testbench.udo
## Created on: Tue Sep 06 16:30:52 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation.
##
######################################################################
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######################################################################
##
## Filename: testbench_wave.fdo
## Created on: Tue Sep 06 17:26:22 W. Europe Daylight Time 2016
##
## Auto generated by Project Navigator for Post-Behavioral Simulation
##
## You may want to edit this file to control your simulation windows.
##
######################################################################
add wave *
#add wave /glbl/GSR
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="pulsetest.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
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......@@ -30,7 +30,8 @@
# source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
#==============================================================================
# last changes:
# 2013-04-26 Theodor Stana t.stana@cern.ch File modified
# 2013-04-26 Theodor Stana t.stana@cern.ch File modified
# 2016-07-25 Denia Bouhired denia.bouhired@cern.ch Added 4 pins connected to inv channel LEDs
#==============================================================================
# TODO: -
#==============================================================================
......
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