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Conv TTL Blocking - Gateware
Commit 5c146616 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Added 4 pins on FPGA (ucf file) to support PCB version recognition

parent 98bb7657
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top/Release/conv_ttl_blo.ucf
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......@@ -32,6 +32,7 @@
# last changes:
# 2013-04-26 Theodor Stana t.stana@cern.ch File modified
# 2016-07-25 Denia Bouhired denia.bouhired@cern.ch Added 4 pins connected to inv channel LEDs
# 2016-07-25 Denia Bouhired denia.bouhired@cern.ch aDDED 4 pins for PCB version recognition
#==============================================================================
# TODO: -
#==============================================================================
......@@ -181,24 +182,35 @@ NET "led_wr_ok_syspw_o" IOSTANDARD = LVCMOS33;
NET "led_wr_ownaddr_i2c_o" LOC = N15;
NET "led_wr_ownaddr_i2c_o" IOSTANDARD = LVCMOS33;
#------------------------------------------------------------------------------
# PCB version pins
#------------------------------------------------------------------------------
NET "pcbrev_i[4]" LOC = T2;
NET "pcbrev_i[4]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[3]" LOC = U3;
NET "pcbrev_i[3]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[2]" LOC = V5;
NET "pcbrev_i[2]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[1]" LOC = W4;
NET "pcbrev_i[1]" IOSTANDARD = LVCMOS33;
NET "pcbrev_i[0]" LOC = T6;
NET "pcbrev_i[0]" IOSTANDARD = LVCMOS33;
#=============================================================================
# Rear panel signals
#=============================================================================
#-----------------------------------------------------------------------------
# Blocking I/O
#-----------------------------------------------------------------------------
NET "blo_i[0]" LOC = Y9;
NET "blo_i[0]" LOC = Y3;
NET "blo_i[0]" IOSTANDARD = LVCMOS33;
NET "blo_i[1]" LOC = AA10;
NET "blo_i[1]" LOC = V3;
NET "blo_i[1]" IOSTANDARD = LVCMOS33;
NET "blo_i[2]" LOC = W12;
NET "blo_i[2]" LOC = P4;
NET "blo_i[2]" IOSTANDARD = LVCMOS33;
NET "blo_i[3]" LOC = AA6;
NET "blo_i[3]" LOC = R4;
NET "blo_i[3]" IOSTANDARD = LVCMOS33;
NET "blo_i[4]" LOC = Y7;
NET "blo_i[4]" IOSTANDARD = LVCMOS33;
NET "blo_i[5]" LOC = AA8;
NET "blo_i[5]" IOSTANDARD = LVCMOS33;
NET "blo_o[0]" LOC = W9;
NET "blo_o[0]" IOSTANDARD = LVCMOS33;
......
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