- 23 Jan, 2015 1 commit
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Theodor-Adrian Stana authored
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- 10 Dec, 2014 1 commit
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Theodor-Adrian Stana authored
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- 30 Sep, 2014 1 commit
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Theodor-Adrian Stana authored
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- 29 Sep, 2014 2 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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- 26 Sep, 2014 3 commits
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Theodor-Adrian Stana authored
The following sections were updated: - 3.1 TTL input logic -- added reflection of no signal detect state in LSR - 3.2 First pulse inhibit -- added delay before enabling the line to conv-common-gw - 3.3 Line input logic -- added reflection of no signal detect state in LSR - 3.4 Switches -- made figure more compact
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Theodor-Adrian Stana authored
Also updated ISE project file to test that nothing went wrong when these modules were deleted.
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Theodor-Adrian Stana authored
The issue with the first pulse inhibit mechanism was (again) that it needs to be disabled one clock cycle after the TTL-BAR no signal detect block is disabled, otherwise the no signal detect block has no effect on the conv-common-gw block, due to sub-modules still being in a reset state. A one-clock-cycle delayed version of inhibit_first_pulse is now used to enable passing the pulse signals to the conv-common-gw block. In addition to this modification, the FRONTFS and FRONTINVFS bits were added to the LSR inside conv-common-gw. The necessary additions were made here to account for the changes in the conv-common-gw interface.
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- 25 Sep, 2014 4 commits
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Theodor-Adrian Stana authored
Also prepared the ISE project file for v3.0 release
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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- 28 Aug, 2014 1 commit
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Theodor-Adrian Stana authored
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- 25 Aug, 2014 1 commit
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Theodor-Adrian Stana authored
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- 22 Aug, 2014 3 commits
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Theodor-Adrian Stana authored
This is done by lighting the LED red when the upper four bits of the gateeware version are "0000".
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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- 21 Aug, 2014 3 commits
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Theodor-Adrian Stana authored
This means we're close to g/w v2.3 (only lacking the documentation)
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Theodor-Adrian Stana authored
general-cores is a submodule of conv-common-gw, and it is from there that all general-cores modules used on top-level are imported
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Theodor-Adrian Stana authored
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- 03 May, 2014 1 commit
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Theodor-Adrian Stana authored
Signed-off-by: Theodor Stana <t.stana@cern.ch>
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- 02 May, 2014 1 commit
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Theodor-Adrian Stana authored
Signed-off-by: Theodor Stana <t.stana@cern.ch>
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- 25 Apr, 2014 1 commit
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Theodor-Adrian Stana authored
Signed-off-by: Theodor Stana <t.stana@cern.ch>
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- 15 Apr, 2014 1 commit
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Theodor-Adrian Stana authored
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- 08 Apr, 2014 2 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
Signed-off-by: Theodor Stana <t.stana@cern.ch>
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- 07 Apr, 2014 2 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
gencores-suproj: fix bug in wb_i2c_slave ctblo_pulse_gen.vhd: add pulse_err_o to signal when a pulse is rejected conv_regs.vhd: add PMISSE and I2C_ERR bits top-level: implement PMISSE and I2C_ERR bits and change error LED logic Signed-off-by: Theodor Stana <t.stana@cern.ch>
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- 28 Mar, 2014 2 commits
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Theodor-Adrian Stana authored
Signed-off-by: Theodor Stana <t.stana@cern.ch>
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Theodor-Adrian Stana authored
Signed-off-by: Theodor Stana <t.stana@cern.ch>
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- 26 Mar, 2014 2 commits
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Theodor-Adrian Stana authored
Signed-off-by: Theodor Stana <t.stana@cern.ch>
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Theodor-Adrian Stana authored
Signed-off-by: Theodor Stana <t.stana@cern.ch>
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- 25 Mar, 2014 1 commit
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Theodor-Adrian Stana authored
hdl: - substitute FIFO for ring buffer - change pulse repetition duty cycle to 1/500 - renamed some files to make "generic" naming sim: - release: add I2C simulation capabilities - conv_pulse_gen: change testbench.vhd for simulating 1/500 duty cycle syn: - update project file with new files Signed-off-by: Theodor Stana <t.stana@cern.ch>
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- 06 Mar, 2014 3 commits
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Theodor-Adrian Stana authored
Signed-off-by: Theodor Stana <t.stana@cern.ch>
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Theodor-Adrian Stana authored
Apart from the .do files which were updated after simulation, the main change is the addition within the main testbench file of a daisy-chain loop on the channel and a couple of assert statements to see if any pulses are missed. Signed-off-by: Theodor Stana <t.stana@cern.ch>
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Theodor-Adrian Stana authored
Signed-off-by: Theodor Stana <t.stana@cern.ch>
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- 05 Mar, 2014 2 commits
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Theodor-Adrian Stana authored
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Theodor-Adrian Stana authored
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- 19 Feb, 2014 1 commit
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Theodor-Adrian Stana authored
Changes: HDL: - added pulse time tagging core (pulse_timetag.vhd) - added FIFO via the conv_regs.wb file - to make the FIFO read work properly, I needed to change the wb_i2c_bridge component (general-cores submodule) - updated top-level to connect the FIFO to conv_regs component - moved the pulse generator glitch filter to outside the pulse generator - changed the conv_pulse_gen block to be able to properly reject pulses up to only 1/5 duty cycle, not more (I realized by simulation that when the glitch filter was enabled, it needed one extra cycle, thus the duty cycle of the pulse was not 1/5, but 1/5 + one clock cycle) - updated synthesis files for the Release project to add the new files, and the regtest and pulsetest due to the I2C bridge changes Simulation files: - conv_pulse_gen: changes for the aforementioned change test - added pulse_timetag sim files - added release top-level simulation, which at the moment does not contain a lot of stuff (only pulse rep test), but can be used as a starter to verify the design works appropriately Doc: - updated memory map with cute wbgen-ized memory map - added time-tagging core information - updated the Getting Around the Code section - added and updated figures Signed-off-by: Theodor Stana <t.stana@cern.ch>
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- 05 Feb, 2014 1 commit
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Theodor-Adrian Stana authored
Also updated hdlguide to reflect this Signed-off-by: Theodor Stana <t.stana@cern.ch>
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