Commit 07db1417 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

hdl: Added one-wire master

Also updated hdlguide to reflect this
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent f943e5f2
......@@ -11,7 +11,7 @@
\hfill Gateware v1.2
\hfill January 30, 2014
\hfill February 5, 2014
\vspace*{3cm}
......
......@@ -196,9 +196,9 @@
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......@@ -628,24 +628,24 @@
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......@@ -734,7 +734,7 @@
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......@@ -1179,5 +1179,62 @@
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@misc{onewire,
author = {Iztok Jeras},
title = {{sockit\_owm, 1-wire (onewire) master}},
year = 2011,
note = {\url{http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf}}
}
@misc{spi,
author = {Simon Srot},
title = {{SPI Master Core Specification}},
......@@ -67,3 +60,16 @@
title = {{Wishbone Slave Generator}},
howpublished = {\url{http://www.ohwr.org/projects/wishbone-gen/wiki}}
}
@misc{onewire-core,
author = {Iztok Jeras},
title = {{sockit\_owm, 1-wire (onewire) master}},
year = 2011,
note = {\url{http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf}}
}
@misc{ds18b20,
author = {{Maxim Integrated}},
title = {{DS18B20 -- Programmable Resolution 1-Wire Digital Thermometer}},
note = {\url{http://datasheets.maximintegrated.com/en/ds/DS18B20.pdf}}
}
......@@ -62,6 +62,7 @@
05-01-2014 & 1.05 & Updated folder structure and renamed \textit{vbcp\_wb} to \textit{i2c\_bridge} \\
28-01-2014 & 1.06 & Added pulse counters in HDL \\
30-01-2014 & 1.07 & Added manual pulse triggering in HDL \\
05-02-2014 & 1.08 & Added one-wire master to HDL \\
\hline
\end{tabular}
}
......@@ -109,10 +110,11 @@ the CONV-TTL-BLO capabilities:
\item fixed-width pulse generation with pulse rejection
\item diagnostics via I$^2$C
\begin{itemize}
\item converter board ID
\item gateware version
\item switches and RTM detection lines
\item pulse counters
\item remote reset
\item unique board ID and temperature readout
\item state of on-board switches and RTM detection lines
\item input pulse counters
\item manual pulse triggering
\end{itemize}
\item remote reprogramming via I$^2$C
......@@ -141,6 +143,7 @@ in the sections that follow.
%==============================================================================
% SEC: Clocks
%==============================================================================
\pagebreak
\section{FPGA clocks}
\label{sec:clocks}
......@@ -177,6 +180,7 @@ Table~\ref{tbl:clocks} lists the clock domains used in the gateware.
%==============================================================================
% SEC: Mem-mapped periphs
%==============================================================================
\pagebreak
\section{Memory-mapped peripherals}
\label{sec:periphs}
......@@ -237,9 +241,25 @@ For information on the module, refer to its documentation. The memory map of the
module is also present in this manual, for quick reference (see
Appendix~\ref{app:memmap-multiboot}).
%------------------------------------------------------------------------------
% SUBSEC: MultiBoot
%------------------------------------------------------------------------------
\subsection{One-wire master}
\label{sec:periphs-onewire}
The one-wire master provides access to the DS18B20 thermometer chip~\cite{ds18b20}
on the CONV-TTL-BLO. It provides two registers for software control of the module.
Note that the FPGA does not control the one-wire thermometer line in any way.
Accessing the thermometer is done through software only.
More details about how to access the one-wire master module can be found in its
documentation~\cite{onewire-core}.
%==============================================================================
% SEC: Reset gen
%==============================================================================
\pagebreak
\section{Reset generator}
\label{sec:reset-gen}
......@@ -286,6 +306,7 @@ By default, the reset time is set to 100~$ms$.
%==============================================================================
% SEC: RTM detection
%==============================================================================
\pagebreak
\section{RTM detection}
\label{sec:rtm-detect}
......@@ -305,7 +326,7 @@ By default, the reset time is set to 100~$ms$.
\vspace*{11pt}
RTM detection is described in \cite{rtm-detect}. Since an RTMM/P missing would mean
RTM detection is described in \cite{rtm-det}. Since an RTMM/P missing would mean
all \textit{rtmm\_i}/\textit{rtmp\_i} lines are all-ones, the \textit{rtm\_detector}
module sets the \textit{rtmm\_ok} and \textit{rtmp\_ok} signals low if the
\textit{rtmm\_i} and \textit{rtmp\_i} input signals are respectively all-ones.
......@@ -324,6 +345,7 @@ can also be read via their respective fields in the converter board status regis
%==============================================================================
% SEC: Bicolor LEDs
%==============================================================================
\pagebreak
\section{Bicolor LED controller}
\label{sec:bicolor-led}
......@@ -548,7 +570,6 @@ on the TTL or blocking channel, or by a manual trigger pulse arriving from the
\label{fig:pulse-brd}
\end{figure}
\pagebreak
Since the \textit{conv\_pulse\_gen} block expects a rising edge at its \textit{trig\_i}
input in order to generate a pulse at the output, logic external to the block
caters for the different types of signals that arrive on CONV-TTL-BLO inputs.
......@@ -604,6 +625,7 @@ the value received via I$^2$C.
%==============================================================================
% SEC: Manual trigger
%==============================================================================
\pagebreak
\section{Manual pulse trigger}
\label{sec:man-trig}
......@@ -638,6 +660,12 @@ numbers should be written. Once this magic sequence has been input, the next wri
the register should be the channel number. If a valid channel number is written,
a pulse is generated on this channel.
\begin{figure}[h]
\centerline{\includegraphics[width=.47\textwidth]{fig/man-trig-fsm}}
\caption{FSM of the \textit{conv\_man\_trig} component}
\label{fig:man-trig-fsm}
\end{figure}
The \textit{conv\_man\_trig} takes the value of the MPT field in the control register
as an input and via the state-machine shown in Figure~\ref{fig:man-trig-fsm}, it checks
that the values written to the MPT field correspond to the magic sequence (Table~\ref{tbl:man-trig-magic}).
......@@ -647,12 +675,6 @@ input of \textit{conv\_pulse\_gen} (see Section~\ref{sec:pulse-gen}) after it is
TTL and blocking inputs as shown in Figure~\ref{fig:pulse-brd}. Should an invalid channel number be
input, no error is reported and no pulse is generated.
\begin{figure}
\centerline{\includegraphics[width=.47\textwidth]{fig/man-trig-fsm}}
\caption{FSM of the \textit{conv\_man\_trig} component}
\label{fig:man-trig-fsm}
\end{figure}
\begin{table}[h]
\caption{Magic sequence to initiate manual pulse triggering}
\label{tbl:man-trig-magic}
......@@ -679,6 +701,7 @@ state (Figure~\ref{fig:man-trig-fsm}).
%======================================================================================
% SEC: Folder structure
%======================================================================================
\pagebreak
\section{Folder structure}
\label{sec:fold-struct}
......@@ -817,6 +840,7 @@ the design and as such can be composed of folders named after the component to b
%======================================================================================
% SEC: Getting Around the Code
%======================================================================================
\pagebreak
\section{Getting around the code}
\label{sec:get-around}
......@@ -923,6 +947,7 @@ $reg. index = \frac{addr}{4} + 1$
\hline
Board regs & 0x000 & 0x020 & Coverter board registers \\
MultiBoot & 0x040 & 0x050 & MultiBoot module \\
Thermo & 0x080 & 0x084 & Thermometer chip \\
\hline
\end{tabular}
}
......@@ -1270,6 +1295,30 @@ $reg. index = \frac{addr}{4} + 1$
\end{tabular}
}
%------------------------------------------------------------------------------
% SUBSEC: Thermo
%------------------------------------------------------------------------------
\subsection{Thermometer module}
\label{app:memmap-thermo}
\indent Base address: 0x080
\vspace*{11pt}
\centerline
{
\begin{tabular}{l l p{.6\textwidth}}
\textbf{Offset} & \textbf{Name} & \textbf{Description} \\
0x00 & OWCSR & One-Wire Control and Status Register \\
0x04 & OWCDR & One-Wire Clock Divider Registers \\
\end{tabular}
}
\vspace*{11pt}
For details on the bits of the thermometer module access registers, see the
OneWire Master module's documentation~\cite{onewire-core}.
%------------------------------------------------------------------------------
\end{appendices}
%------------------------------------------------------------------------------
......
......@@ -175,44 +175,50 @@ architecture behav of conv_ttl_blo is
-- next minor release v1.1 c_gwvers = x"11";
-- 13 minor releases later v1.14 c_gwvers = x"1e";
-- next major release v2.0 c_gwvers = x"20";
constant c_gwvers : std_logic_vector(7 downto 0) := x"12";
constant c_gwvers : std_logic_vector(7 downto 0) := x"13";
-- Number of Wishbone masters and slaves, for wb_crossbar
constant c_nr_masters : natural := 1;
constant c_nr_slaves : natural := 2;
constant c_nr_slaves : natural := 3;
------------------------------------------------------------------------------
-- Memory map
-- * all registers are word-addressable
-- * all registers are word-aligned
------------------------------------------------------------------------------
-- CONV_REGS [000-040]
-- MULTIBOOT [040-080]
-- CONV_REGS [000-020]
-- MULTIBOOT [040-050]
-- ONEWIRE [080-]
------------------------------------------------------------------------------
-- slave order definitions
constant c_slv_conv_regs : natural := 0;
constant c_slv_multiboot : natural := 1;
constant c_slv_conv_regs : natural := 0;
constant c_slv_multiboot : natural := 1;
constant c_slv_onewire_mst : natural := 2;
-- base address definitions
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_multiboot : t_wishbone_address := x"00000040";
constant c_addr_conv_regs : t_wishbone_address := x"00000000";
constant c_addr_multiboot : t_wishbone_address := x"00000040";
constant c_addr_onewire_mst : t_wishbone_address := x"00000080";
-- address mask definitions
constant c_mask_conv_regs : t_wishbone_address := x"00000fc0";
constant c_mask_multiboot : t_wishbone_address := x"00000fc0";
constant c_mask_conv_regs : t_wishbone_address := x"00000fc0";
constant c_mask_multiboot : t_wishbone_address := x"00000fc0";
constant c_mask_onewire_mst : t_wishbone_address := x"00000fe0";
-- addresses constant for Wishbone crossbar
constant c_addresses : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_addr_conv_regs,
c_slv_multiboot => c_addr_multiboot
c_slv_conv_regs => c_addr_conv_regs,
c_slv_multiboot => c_addr_multiboot,
c_slv_onewire_mst => c_addr_onewire_mst
);
-- masks constant for Wishbone crossbar
constant c_masks : t_wishbone_address_array(c_nr_slaves-1 downto 0)
:= (
c_slv_conv_regs => c_mask_conv_regs,
c_slv_multiboot => c_mask_multiboot
c_slv_conv_regs => c_mask_conv_regs,
c_slv_multiboot => c_mask_multiboot,
c_slv_onewire_mst => c_mask_onewire_mst
);
------------------------------------------------------------------------------
......@@ -434,6 +440,12 @@ architecture behav of conv_ttl_blo is
signal rtmm, rtmp : std_logic_vector(2 downto 0);
signal rtmm_ok, rtmp_ok : std_logic;
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- Signals to/from converter system registers component
signal rtm_lines : std_logic_vector(5 downto 0);
signal switches_n : std_logic_vector(7 downto 0);
......@@ -446,6 +458,10 @@ architecture behav of conv_ttl_blo is
signal mpt_ld : std_logic;
signal mpt : std_logic_vector(7 downto 0);
-- One-wire master signals
signal owr_en : std_logic_vector(0 downto 0);
signal owr_in : std_logic_vector(0 downto 0);
-- Signals for pulse generation triggers
signal trig_a : std_logic_vector(g_nr_ttl_chan downto 1);
signal trig_ttl_a : std_logic_vector(g_nr_ttl_chan downto 1);
......@@ -477,12 +493,6 @@ architecture behav of conv_ttl_blo is
-- Signal for controlling the bicolor LED matrix
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- Wishbone crossbar signals
signal xbar_slave_in : t_wishbone_slave_in_array (c_nr_masters - 1 downto 0);
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- I2C bridge signals
signal i2c_tip : std_logic;
signal i2c_err_p : std_logic;
......@@ -917,6 +927,46 @@ begin
spi_miso_i => fpga_prom_miso_i
);
--============================================================================
-- On-board DS18B20 Thermometer logic
--============================================================================
-- The one-wire master component is used to control the on-board DS18B20
-- thermometer
cmp_onewire_master : wb_onewire_master
generic map
(
g_interface_mode => CLASSIC,
g_address_granularity => WORD,
g_num_ports => 1,
g_ow_btp_normal => "5.0",
g_ow_btp_overdrive => "1.0"
)
port map
(
clk_sys_i => clk20_vcxo_i,
rst_n_i => rst_n,
wb_cyc_i => xbar_master_out(c_slv_onewire_mst).cyc,
wb_sel_i => xbar_master_out(c_slv_onewire_mst).sel,
wb_stb_i => xbar_master_out(c_slv_onewire_mst).stb,
wb_we_i => xbar_master_out(c_slv_onewire_mst).we,
wb_adr_i => xbar_master_out(c_slv_onewire_mst).adr(4 downto 2),
wb_dat_i => xbar_master_out(c_slv_onewire_mst).dat,
wb_dat_o => xbar_master_in(c_slv_onewire_mst).dat,
wb_ack_o => xbar_master_in(c_slv_onewire_mst).ack,
wb_int_o => open,
wb_stall_o => xbar_master_in(c_slv_onewire_mst).stall,
owr_pwren_o => open,
owr_en_o => owr_en,
owr_i => owr_in
);
-- Generate tri-state buffer for thermometer
thermometer_b <= '0' when (owr_en(0) = '1') else
'Z';
owr_in(0) <= thermometer_b;
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
......@@ -1008,9 +1058,6 @@ begin
--============================================================================
-- Drive unused outputs with safe values
--============================================================================
-- Theremometer output to high-impedance
thermometer_b <= 'Z';
-- DAC outputs: enables to '1' (disable DAC comm interface) and SCK, DIN to '0'
fpga_plldac1_sync_n_o <= '1';
fpga_plldac1_din_o <= '0';
......
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