Commit 1b4de266 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Fixed inhibit first pulse and added FRONTFS and FRONTINVFS bits in LSR

The issue with the first pulse inhibit mechanism was (again) that it needs
to be disabled one clock cycle after the TTL-BAR no signal detect block is disabled,
otherwise the no signal detect block has no effect on the conv-common-gw block, due
to sub-modules still being in a reset state.

A one-clock-cycle delayed version of inhibit_first_pulse is now used to enable passing
the pulse signals to the conv-common-gw block.

In addition to this modification, the FRONTFS and FRONTINVFS bits were added
to the LSR inside conv-common-gw. The necessary additions were made here to
account for the changes in the conv-common-gw interface.
parent a38310df
conv-common-gw @ dc4bfb25
Subproject commit d69919e6ec11e93fdf1528b2aae5e356c0bd2d8d
Subproject commit dc4bfb2545abd9c8cc3851a33839804afd470116
......@@ -184,6 +184,7 @@ architecture arch of conv_ttl_blo is
signal pulse_ttl : std_logic_vector(c_nr_chans-1 downto 0);
signal pulse_blo : std_logic_vector(c_nr_chans-1 downto 0);
signal inhibit_first_pulse : std_logic;
signal inhibit_first_pulse_d0 : std_logic;
signal inhibit_cnt : unsigned(10 downto 0);
-- Line signals -- for reflection in line status register of conv_common_gw
......@@ -197,7 +198,7 @@ architecture arch of conv_ttl_blo is
-- No signal on TTL-BAR
signal ttlbar_nosig_cnt : t_ttlbar_nosig_cnt;
signal ttlbar_nosig_n : std_logic_vector(c_nr_chans-1 downto 0);
signal ttlbar_nosig : std_logic_vector(c_nr_chans-1 downto 0);
-- Channel LED signals
signal led_pulse : std_logic_vector(c_nr_chans-1 downto 0);
......@@ -228,7 +229,7 @@ begin
-- The "no signal detect" block
--
-- If the signal line is high for 100 us, the ttlbar_nosig_n lines disable
-- If the signal line is high for 100 us, the ttlbar_nosig lines disable
-- the input to the TTL side MUX and the OR gate.
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
......@@ -238,12 +239,12 @@ begin
if rising_edge(clk_20_i) then
for i in 0 to c_nr_chans-1 loop
if (rst_20_n = '0') or (ttl_n_i(i) = '0') then
ttlbar_nosig_n(i) <= '1';
ttlbar_nosig(i) <= '0';
ttlbar_nosig_cnt(i) <= (others => '0');
elsif (sw_ttl = '0') then
ttlbar_nosig_cnt(i) <= ttlbar_nosig_cnt(i) + 1;
if (ttlbar_nosig_cnt(i) = 1999) then
ttlbar_nosig_n(i) <= '0';
ttlbar_nosig(i) <= '1';
ttlbar_nosig_cnt(i) <= (others => '0');
end if;
end if;
......@@ -253,7 +254,7 @@ begin
-- TTL and blocking inputs
pulse_ttl <= not ttl_n_i when sw_ttl = '1' else
ttl_n_i and ttlbar_nosig_n;
ttl_n_i and (not ttlbar_nosig);
pulse_blo <= blo_i;
......@@ -275,8 +276,21 @@ begin
end if;
end process p_inhibit_first_pulse;
-- Delay inhibit first pulse signal, use this to enable input, thus avoiding
-- internal reset states of conv_common_gw
p_inhibit_first_pulse_d0 : process (clk_20_i)
begin
if rising_edge(clk_20_i) then
if (rst_20_n = '0') then
inhibit_first_pulse_d0 <= '1';
else
inhibit_first_pulse_d0 <= inhibit_first_pulse;
end if;
end if;
end process;
-- Pulse input valid only after inhibit period is over
pulse_in <= (pulse_ttl or pulse_blo) when (inhibit_first_pulse = '0') else
pulse_in <= (pulse_ttl or pulse_blo) when (inhibit_first_pulse_d0 = '0') else
(others => '0');
-- Line inputs for reflection in status register
......@@ -389,6 +403,10 @@ begin
line_front_i => line_ttl,
line_inv_i => line_invttl,
line_rear_i => line_blo,
-- Fail-safe lines, detect invalid or no signal on channel input
line_front_fs_i => ttlbar_nosig,
line_inv_fs_i => (others => '0'),
line_rear_fs_i => (others => '0'),
-- Thermometer line
......
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