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C
Conv TTL Blocking - Gateware
Commit a38310df authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Changed MSWR name to OSWR in conv-common-gw 

Also prepared the ISE project file for v3.0 release
parent 1e391536
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conv-common-gw @ d69919e6
Subproject commit f45a637fd760fa2c5feb7c84313c2ff6e84698f5
Subproject commit d69919e6ec11e93fdf1528b2aae5e356c0bd2d8d
syn/Release/conv_ttl_blo.xise
View file @ a38310df
......@@ -175,7 +175,7 @@
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="-g next_config_register_write:Disable" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -202,7 +202,7 @@
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
......
top/Release/conv_ttl_blo.vhd
View file @ a38310df
......@@ -164,7 +164,7 @@ architecture arch of conv_ttl_blo is
constant c_board_id : std_logic_vector(31 downto 0) := x"54424c4f";
-- Gateware version
constant c_gwvers : std_logic_vector(7 downto 0) := x"02";
constant c_gwvers : std_logic_vector(7 downto 0) := x"30";
--============================================================================
-- Type declarations
......@@ -301,11 +301,11 @@ begin
g_pgen_pwidth => 24,
g_pgen_duty_cycle_div => 200,
g_pgen_gf_len => 1,
-- g_with_pulse_cnt => true,
-- g_with_pulse_timetag => true,
-- g_with_man_trig => true,
-- g_man_trig_pwidth => 24,
-- g_with_thermometer => true,
g_with_pulse_cnt => true,
g_with_pulse_timetag => true,
g_with_man_trig => true,
g_man_trig_pwidth => 24,
g_with_thermometer => true,
g_bicolor_led_columns => c_bicolor_led_cols,
g_bicolor_led_lines => c_bicolor_led_lines
)
......@@ -379,7 +379,7 @@ begin
-- Switch inputs (for readout from converter status register)
sw_gp_i => sw_gp,
sw_multicast_i => (others => '0'),
sw_other_i => (others => '0'),
-- RTM lines
rtmm_i => rtmm_i,
......
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