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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
8f1150d5
Commit
8f1150d5
authored
Aug 22, 2014
by
Theodor-Adrian Stana
Browse files
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Moved some simulation models to conv-common-gw and deleted the rest
parent
2cf1817b
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976 deletions
+1
-976
conv-common-gw
ip_cores/conv-common-gw
+1
-1
run.do
sim/conv_man_trig/run.do
+0
-21
testbench.vhd
sim/conv_man_trig/testbench.vhd
+0
-355
wave.do
sim/conv_man_trig/wave.do
+0
-51
run.do
sim/conv_pulse_gen/run.do
+0
-22
testbench.vhd
sim/conv_pulse_gen/testbench.vhd
+0
-239
wave.do
sim/conv_pulse_gen/wave.do
+0
-34
run.do
sim/pulse_timetag/run.do
+0
-19
testbench.vhd
sim/pulse_timetag/testbench.vhd
+0
-234
No files found.
conv-common-gw
@
07ba0838
Subproject commit
183c2bae08345d564371299c0aa0f00d227789ed
Subproject commit
07ba08381feec856a8a94951fed10c42bbc0d871
sim/conv_man_trig/run.do
deleted
100644 → 0
View file @
2cf1817b
vlib work
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../modules/Release/conv_pulse_gen.vhd"
vcom -explicit -93 "../../modules/Release/conv_man_trig.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
# add wave *
do wave.do
run 300 us
wave zoomfull
sim/conv_man_trig/testbench.vhd
deleted
100644 → 0
View file @
2cf1817b
This diff is collapsed.
Click to expand it.
sim/conv_man_trig/wave.do
deleted
100644 → 0
View file @
2cf1817b
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk20
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/mpt_ld
add wave -noupdate /testbench/mpt
add wave -noupdate /testbench/trig_man
add wave -noupdate -expand /testbench/pulse
add wave -noupdate -divider DUT
add wave -noupdate /testbench/cmp_dut/state
add wave -noupdate /testbench/cmp_dut/pass
add wave -noupdate /testbench/cmp_dut/chnr
add wave -noupdate /testbench/cmp_dut/cnt
add wave -noupdate /testbench/cmp_dut/trig_o
add wave -noupdate -divider {glitch filt}
add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/gf_en_n_i
add wave -noupdate -divider {pulse gen}
add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(1)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(2)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(3)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(4)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(5)/cmp_pulse_gen/pulse_gf_on
add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/pulse_gf_off
add wave -noupdate /testbench/gen_pulse_gens(6)/cmp_pulse_gen/pulse_gf_on
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {218986486 ps} 0} {{Cursor 2} {74966216 ps} 0}
configure wave -namecolwidth 383
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {315 us}
sim/conv_pulse_gen/run.do
deleted
100644 → 0
View file @
2cf1817b
vlib work
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../modules/pulsetest/pulse_gen_gp.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../modules/Release/conv_pulse_gen.vhd"
vcom -explicit -93 "../../modules/Release/conv_man_trig.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
# add wave *
do wave.do
run 10 ms
wave zoomfull
sim/conv_pulse_gen/testbench.vhd
deleted
100644 → 0
View file @
2cf1817b
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for old repeater design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
gencores_pkg
.
all
;
entity
testbench
is
end
entity
testbench
;
architecture
behav
of
testbench
is
--============================================================================
-- Constant declarations
--============================================================================
constant
c_clk_per
:
time
:
=
50
ns
;
constant
c_reset_width
:
time
:
=
31
ns
;
--============================================================================
-- Component declarations
--============================================================================
component
conv_pulse_gen
is
generic
(
-- Pulse width, in number of clk_i cycles
-- Default pulse width (20 MHz clock): 1.2 us
-- Minimum allowable pulse width (20 MHz clock): 1 us
-- Maximum allowable pulse width (20 MHz clock): 2 us
g_pwidth
:
natural
range
20
to
40
:
=
24
;
-- Duty cycle divider: D = 1/g_duty_cycle_div
g_duty_cycle_div
:
natural
:
=
5
);
port
(
-- Clock and active-low reset inputs
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Glitch filter enable input
-- '1' - Glitch filter disabled (glitch-sensitive, no output jitter)
-- '0' - Glitch filter enabled (glitch-insensitive, with output jitter)
gf_en_n_i
:
in
std_logic
;
-- Enable input, pulse generation is enabled when '1'
en_i
:
in
std_logic
;
-- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays.
trig_a_i
:
in
std_logic
;
-- Pulse output, active-high
-- latency:
-- glitch filter disabled: none
-- glitch filter enabled: glitch filter length + 5 clk_i cycles
pulse_o
:
out
std_logic
);
end
component
conv_pulse_gen
;
component
pulse_gen_gp
is
port
(
-- Input clock and active-low reset
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Active high enable signal
en_i
:
in
std_logic
;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i
:
in
std_logic_vector
(
31
downto
0
);
pwidth_i
:
in
std_logic_vector
(
31
downto
0
);
freq_i
:
in
std_logic_vector
(
31
downto
0
);
-- Output pulse signal
pulse_o
:
out
std_logic
);
end
component
pulse_gen_gp
;
--============================================================================
-- Signal declarations
--============================================================================
signal
clk
,
clk4
,
rst_n
,
pulse
,
trig
,
lvl
,
lvl_n
:
std_logic
:
=
'0'
;
signal
trig_degl
:
std_logic
;
signal
trig_chan
:
std_logic
;
signal
trig_man
:
std_logic
;
signal
actual_trig
:
std_logic
:
=
'0'
;
signal
actual_pulse
:
std_logic
:
=
'0'
;
signal
gf_en
:
std_logic
;
signal
gf_en_n
:
std_logic
;
signal
pgen_en
:
std_logic
;
--==============================================================================
-- architecture begin
--==============================================================================
begin
-- DUT INSTANTIATION
DUT
:
conv_pulse_gen
generic
map
(
g_pwidth
=>
24
,
g_duty_cycle_div
=>
500
)
port
map
(
clk_i
=>
clk
,
rst_n_i
=>
rst_n
,
gf_en_n_i
=>
gf_en_n
,
en_i
=>
'1'
,
trig_a_i
=>
actual_trig
,
pulse_o
=>
pulse
);
-- CLOCK GENERATION
p_clk
:
process
begin
clk
<=
not
clk
;
wait
for
c_clk_per
/
2
;
end
process
p_clk
;
-- SECOND CLOCK GENERATION
p_clk4
:
process
begin
clk4
<=
not
clk4
;
wait
for
2
ns
;
end
process
p_clk4
;
-- RESET GENERATION
p_rst_n
:
process
begin
rst_n
<=
'0'
;
wait
for
c_reset_width
;
rst_n
<=
'1'
;
wait
;
end
process
p_rst_n
;
-- PULSE GENERATOR FOR TRIGGER
cmp_pulse_gen
:
pulse_gen_gp
port
map
(
clk_i
=>
clk4
,
rst_n_i
=>
rst_n
,
en_i
=>
pgen_en
,
delay_i
=>
(
others
=>
'0'
),
pwidth_i
=>
x"0000012c"
,
freq_i
=>
x"000249f0"
,
pulse_o
=>
trig
);
-- Glitch filter instantiation
cmp_gf
:
gc_glitch_filt
generic
map
(
g_len
=>
1
)
port
map
(
clk_i
=>
clk
,
rst_n_i
=>
rst_n
,
dat_i
=>
trig
,
dat_o
=>
trig_degl
);
-- Trigger signal
trig_chan
<=
trig
when
gf_en_n
=
'1'
else
trig_degl
;
actual_trig
<=
trig_chan
or
trig_man
;
-- Glitch filter enable
gf_en_n
<=
'0'
;
-- manual trigger stimuli
p_man_trig
:
process
begin
trig_man
<=
'0'
;
pgen_en
<=
'0'
;
wait
for
10
us
;
trig_man
<=
'1'
;
wait
for
c_clk_per
;
trig_man
<=
'0'
;
wait
for
10
us
;
trig_man
<=
'1'
;
wait
for
c_clk_per
;
trig_man
<=
'0'
;
wait
for
10
us
;
pgen_en
<=
'1'
;
-- wait for 30 us;
-- pgen_en <= '0';
-- wait for 10 us;
-- trig_man <= '1';
-- wait for c_clk_per;
-- trig_man <= '0';
-- wait for 10 us;
-- pgen_en <= '1';
wait
;
end
process
;
end
architecture
behav
;
--==============================================================================
-- architecture end
--==============================================================================
sim/conv_pulse_gen/wave.do
deleted
100644 → 0
View file @
2cf1817b
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/trig
add wave -noupdate /testbench/trig_man
add wave -noupdate /testbench/actual_trig
add wave -noupdate /testbench/actual_pulse
add wave -noupdate /testbench/gf_en_n
add wave -noupdate -divider ctb_pulse_gen
add wave -noupdate /testbench/DUT/pulse_o
add wave -noupdate /testbench/DUT/trig_a_i
add wave -noupdate /testbench/DUT/state
add wave -noupdate /testbench/DUT/pulse_cnt
add wave -noupdate /testbench/DUT/pulse_gf_on
add wave -noupdate /testbench/DUT/pulse_gf_off
add wave -noupdate /testbench/DUT/pulse_gf_off_rst
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2711183 ps} 0} {{Cursor 2} {23915869 ps} 0}
configure wave -namecolwidth 253
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {105 us}
sim/pulse_timetag/run.do
deleted
100644 → 0
View file @
2cf1817b
vlib work
vcom -explicit -93 "../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gencores_pkg.vhd"
vcom -explicit -93 "../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd"
vcom -explicit -93 "../../modules/Release/pulse_timetag.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
add wave *
#do wave.do
run 100 us
wave zoomfull
sim/pulse_timetag/testbench.vhd
deleted
100644 → 0
View file @
2cf1817b
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for pulse time-tagging core
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2014-02-06
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2014-02-06 Theodor Stana File created
--==============================================================================
-- TODO: -
--==============================================================================
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
gencores_pkg
.
all
;
entity
testbench
is
end
entity
testbench
;
architecture
behav
of
testbench
is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant
c_clk_20_per
:
time
:
=
50
ns
;
constant
c_clk_125_per
:
time
:
=
8
ns
;
constant
c_reset_width
:
time
:
=
31
ns
;
--============================================================================
-- Component declarations
--============================================================================
-- DUT component
component
pulse_timetag
is
generic
(
-- Frequency in Hz of the clk_i signal
g_clk_rate
:
positive
:
=
125000000
;
-- Number of repetition channels
g_nr_chan
:
positive
:
=
6
);
port
(
-- Clock and active-low reset
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Asynchronous pulse input
pulse_a_i
:
in
std_logic_vector
(
g_nr_chan
-1
downto
0
);
-- Time inputs from White Rabbit
wr_tm_cycles_i
:
in
std_logic_vector
(
27
downto
0
);
wr_tm_tai_i
:
in
std_logic_vector
(
39
downto
0
);
wr_tm_valid_i
:
in
std_logic
;
-- Timing inputs from Wishbone-mapped registers
wb_tm_tai_l_i
:
in
std_logic_vector
(
31
downto
0
);
wb_tm_tai_l_ld_i
:
in
std_logic
;
wb_tm_tai_h_i
:
in
std_logic_vector
(
7
downto
0
);
wb_tm_tai_h_ld_i
:
in
std_logic
;
-- Timing outputs
tm_cycles_o
:
out
std_logic_vector
(
27
downto
0
);
tm_tai_o
:
out
std_logic_vector
(
39
downto
0
)
);
end
component
pulse_timetag
;
--============================================================================
-- Signal declarations
--============================================================================
-- Clock, reset signals
signal
clk_20
,
clk_125
:
std_logic
;
signal
rst_20_n
,
rst_125_n
:
std_logic
;
-- Register signals to/from "Wishbone"
signal
tvlr_ld
,
tvhr_ld
:
std_logic
;
signal
ldh
,
ldl
:
std_logic
;
signal
tvlr
,
l
:
std_logic_vector
(
31
downto
0
);
signal
tvhr
,
h
:
std_logic_vector
(
7
downto
0
);
-- Cycles, TAI and tick to "Wishbone"
signal
tm_cycles
:
std_logic_vector
(
27
downto
0
);
signal
tm_tai
:
std_logic_vector
(
39
downto
0
);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- DUT instantiation
--============================================================================
cmp_dut
:
pulse_timetag
generic
map
(
g_clk_rate
=>
125000000
,
g_nr_chan
=>
6
)
port
map
(
clk_i
=>
clk_125
,
rst_n_i
=>
rst_125_n
,
pulse_a_i
=>
(
others
=>
'0'
),
wr_tm_cycles_i
=>
(
others
=>
'0'
),
wr_tm_tai_i
=>
(
others
=>
'0'
),
wr_tm_valid_i
=>
'0'
,
wb_tm_tai_l_i
=>
tvlr
,
wb_tm_tai_l_ld_i
=>
tvlr_ld
,
wb_tm_tai_h_i
=>
tvhr
,
wb_tm_tai_h_ld_i
=>
tvhr_ld
,
tm_cycles_o
=>
tm_cycles
,
tm_tai_o
=>
tm_tai
);
--============================================================================
-- Clock and reset generation
--============================================================================
p_clk_20
:
process
begin
clk_20
<=
'0'
;
wait
for
c_clk_20_per
/
2
;
clk_20
<=
'1'
;
wait
for
c_clk_20_per
/
2
;
end
process
p_clk_20
;
p_clk_125
:
process
begin
clk_125
<=
'0'
;
wait
for
c_clk_125_per
/
2
;
clk_125
<=
'1'
;
wait
for
c_clk_125_per
/
2
;
end
process
p_clk_125
;
p_rst_20_n
:
process
begin
rst_20_n
<=
'0'
;
wait
for
c_reset_width
;
wait
for
c_clk_20_per
;
rst_20_n
<=
'1'
;
wait
;
end
process
p_rst_20_n
;
cmp_sync_rst
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_125
,
rst_n_i
=>
'1'
,
data_i
=>
rst_20_n
,
synced_o
=>
rst_125_n
);
--============================================================================
-- Stimuli
--============================================================================
-- Stimuli process
p_stim
:
process
begin
l
<=
(
others
=>
'0'
);
h
<=
(
others
=>
'0'
);
ldh
<=
'0'
;
ldl
<=
'0'
;
wait
for
1
us
;
l
<=
x"0000f000"
;
ldl
<=
'1'
;
wait
for
c_clk_20_per
;
ldl
<=
'0'
;
wait
for
1
us
;
h
<=
x"01"
;
ldh
<=
'1'
;
wait
for
c_clk_20_per
;
ldh
<=
'0'
;
wait
;
end
process
p_stim
;
-- Set the TVR on clock boundaries
p_tvr
:
process
(
clk_20
)
begin
if
rising_edge
(
clk_20
)
then
if
rst_20_n
=
'0'
then
tvlr
<=
(
others
=>
'0'
);
tvhr
<=
(
others
=>
'0'
);
tvlr_ld
<=
'0'
;
tvhr_ld
<=
'0'
;
elsif
ldl
=
'1'
then
tvlr
<=
l
;
tvlr_ld
<=
'1'
;
elsif
ldh
=
'1'
then
tvhr
<=
h
;
tvhr_ld
<=
'1'
;
else
tvlr_ld
<=
'0'
;
tvhr_ld
<=
'0'
;
end
if
;
end
if
;
end
process
p_tvr
;
end
architecture
behav
;
--==============================================================================
-- architecture end
--==============================================================================
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