Commits · fe045ba66f44a4cc9f047726015c2f5a7fbbf2bc · Projects / White Rabbit core collection · Open Hardware Repository

14 Feb, 2017 6 commits
- cleanup and improvements to reduce number of warnings generated by some of the cores · fe045ba6
  Dimitris Lampridis authored Feb 14, 2017
  
  fe045ba6
- modules/wr_endpoint: sanitise monitoring of link activity · 34bd6f04
  Dimitris Lampridis authored Feb 02, 2017
  
  34bd6f04
- modules/wr_endpoint: keep PHY reset when SFP reports LOS · 116c61a4
  Dimitris Lampridis authored Feb 02, 2017
  
  116c61a4
- modules/wr_endpoint: pulse synchroniser for pfilter_done should use the rx clock reset (input side) · e4a21ea1
  Dimitris Lampridis authored Feb 02, 2017
  
  e4a21ea1
- ip_cores: add vme64x-core (for SVEC and VFC-HD reference designs) · 7b34c90c
  Dimitris Lampridis authored Feb 01, 2017
  
  7b34c90c
- use optimized DPRAM for faster initialization during WRPC synthesis · 912b3cad
  Grzegorz Daniluk authored Feb 14, 2017
  
  912b3cad
26 Jan, 2017 4 commits
- testbench: Generate test_results.xml for CI · 28fd3d67
  Adam Wujek authored Jan 26, 2017
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  28fd3d67
- Merge branch 'minic_fifo' into proposed_master · 7d17ce87
  Grzegorz Daniluk authored Jan 26, 2017
  
  7d17ce87
- update wrc.ram for new fifo-based Minic · 934eb7ff
  Grzegorz Daniluk authored Jan 26, 2017
```
Compiled from wrpc-sw:
1c028e8e Merge branch 'minic_fifo' into proposed_master
```
  934eb7ff
- optimize WB crossbar connections · b7ed01ea
  Grzegorz Daniluk authored Jan 26, 2017
  
  b7ed01ea
25 Jan, 2017 4 commits
- wr_core: use one DPRAM port for LM32 instruction bus · d722e794
  Grzegorz Daniluk authored Jan 25, 2017
  
  d722e794
- Merge branch 'greg-testbenches' into minic_fifo · 189cbac1
  Grzegorz Daniluk authored Jan 25, 2017
  
  189cbac1
- remove unused signals after Minic started using FIFOs · 1117a9a3
  Grzegorz Daniluk authored Jan 25, 2017
  
  1117a9a3
- BUFG and BUFIO2 standard Xilinx components don't need declarations · bad54c60
  Grzegorz Daniluk authored Jan 24, 2017
```
This also removes Xilinx ISE synthesis warnings like:
wr-cores\platform\xilinx\wr_gtp_phy\wr_gtp_phy_spartan6.vhd" Line 246: <bufio2>
remains a black-box since it has no binding entity.
```
  bad54c60
24 Jan, 2017 5 commits
- testbench/wrc_core: update testbench for Continuous Integration · 5f29bdf3
  Grzegorz Daniluk authored Jan 24, 2017
  
  5f29bdf3
- testbench: Create Makefile to be used by CI · 903ba03a
  Adam Wujek authored Jan 23, 2017
```
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
```
  903ba03a
- testbench/wr_minic: add simple SV functional coverage analysis · b18df73e
  Grzegorz Daniluk authored Jan 24, 2017
  
  b18df73e
- testbench/wr_minic: cleanup, test Tx and Rx path in the same time · 0ac188c8
  Grzegorz Daniluk authored Jan 24, 2017
  
  0ac188c8
- sim/minic_drv: make Tx and Rx printouts look similar · af24ca6d
  Grzegorz Daniluk authored Jan 24, 2017
  
  af24ca6d
20 Jan, 2017 3 commits
- testbench/wr_minic: adding run_ci.do for continuous integration · b7bb7b6d
  Grzegorz Daniluk authored Jan 20, 2017
  
  b7bb7b6d
- update general-cores submodule · eaa4a6d8
  Grzegorz Daniluk authored Jan 20, 2017
  
  eaa4a6d8
- update testbeches Manifests to use new hdlmake · 10ccc8c1
  Grzegorz Daniluk authored Jan 20, 2017
  
  10ccc8c1
22 Nov, 2016 16 commits
- minic: update testbench to test Tx/Rx FIFOs · 486137e9
  Grzegorz Daniluk authored Nov 03, 2016
  
  486137e9
- sim: update packet sink/source to send/receive RX OOB · 6be7824c
  Grzegorz Daniluk authored Nov 03, 2016
  
  6be7824c
- sim: update minic driver for receiving frames · adcb8584
  Grzegorz Daniluk authored Nov 03, 2016
  
  adcb8584
- wr_core: use new minic with FIFOs · 89e028ef
  Grzegorz Daniluk authored Nov 03, 2016
  
  89e028ef
- minic: generate also *.h with wbgen · cc3a501c
  Grzegorz Daniluk authored Nov 03, 2016
  
  cc3a501c
- minic: FIFO FSMs bugfixes after testing in hardware · 3f6f8289
  Grzegorz Daniluk authored Nov 03, 2016
  
  3f6f8289
- minic: removing legacy code · e0d07f9e
  Grzegorz Daniluk authored Oct 27, 2016
  
  e0d07f9e
- minic: generate tx and rx irqs · 2093ae86
  Grzegorz Daniluk authored Oct 27, 2016
  
  2093ae86
- minic: support big and little endian · ca539d2a
  Grzegorz Daniluk authored Oct 27, 2016
  
  ca539d2a
- minic: Rx path rewritten with FIFO · 264f1d32
  Grzegorz Daniluk authored Oct 27, 2016
  
  264f1d32
- minic: removing legacy TX path stuff · e6f4073e
  Grzegorz Daniluk authored Oct 25, 2016
  
  e6f4073e
- minic: Tx path fixes after simulation · b6b116bb
  Grzegorz Daniluk authored Oct 25, 2016
  
  b6b116bb
- minic: updating simulation and testbench for fifos · 05fc2bee
  Grzegorz Daniluk authored Oct 18, 2016
  
  05fc2bee
- minic: Tx path rewritten with FIFO · b670fedb
  Grzegorz Daniluk authored Oct 18, 2016
  
  b670fedb
- minic: work in progress, use fifos · 443c0581
  Grzegorz Daniluk authored Oct 12, 2016
  
  443c0581
- move phy records to endpoint package and use them for WRPC · 3c2a6c72
  Grzegorz Daniluk authored Nov 22, 2016
  
  3c2a6c72
21 Nov, 2016 2 commits
- removed from streamers dependency on WR-Btrain specific package · 65a8bda9
  Maciej Lipinski authored Nov 21, 2016
  
  65a8bda9
- wr_endpoints: missing default values for signals that are optional · 8f3dcfd5
  Grzegorz Daniluk authored Nov 21, 2016
  
  8f3dcfd5