modules/wr_endpoint: sanitise monitoring of link activity

34bd6f04 · Dimitris Lampridis · 116c61a4 · 34bd6f04 · 34bd6f04
Commit 34bd6f04 authored Feb 02, 2017 by Dimitris Lampridis
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ep_leds_controller.vhd modules/wr_endpoint/ep_leds_controller.vhd +3 -10

wr_endpoint.vhd modules/wr_endpoint/wr_endpoint.vhd +7 -10

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--- a/modules/wr_endpoint/ep_leds_controller.vhd
+++ b/modules/wr_endpoint/ep_leds_controller.vhd
@@ -35,20 +35,13 @@ architecture rtl of ep_leds_controller is
  signal state                  : t_state;
  signal led_act                : std_logic;
  signal last_cycle_act         : std_logic;
-  signal txrx, txrx_synced      : std_logic;
+  signal txrx                   : std_logic;
 begin  -- rtl

  led_link_o <= link_ok_i;

  txrx <= dvalid_rx_i or dvalid_tx_i;

-  U_Sync_Activity : gc_sync_ffs
-    port map (
-      clk_i    => clk_sys_i,
-      rst_n_i  => rst_n_i,
-      data_i   => txrx,
-      synced_o => txrx_synced);
-
  p_counter : process(clk_sys_i)
  begin
    if rising_edge(clk_sys_i) then
@@ -76,7 +69,7 @@ begin  -- rtl
      else
        case state is
          when INACTIVE =>
-            if(txrx_synced = '1') then
+            if(txrx = '1') then
              state     <= BLINKING;
              led_act   <= '1';
              cnt_reset <= '1';
@@ -91,7 +84,7 @@ begin  -- rtl
              end if;
              last_cycle_act <= '0';
            else
-              if(txrx_synced = '1') then
+              if(txrx = '1') then
                last_cycle_act <= '1';
              end if;
            end if;

--- a/modules/wr_endpoint/wr_endpoint.vhd
+++ b/modules/wr_endpoint/wr_endpoint.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN BE-CO-HT
 -- Created    : 2010-04-26
-- Last update: 2013-03-15
+-- Last update: 2017-02-02
 -- Platform   : FPGA-generics
 -- Standard   : VHDL
 -------------------------------------------------------------------------------
@@ -20,7 +20,7 @@
 -- Refer to the manual for more details.
 -------------------------------------------------------------------------------
 --
-- Copyright (c) 2011 - 2012 CERN / BE-CO-HT
+-- Copyright (c) 2011 - 2017 CERN / BE-CO-HT
 --
 -- This source file is free software; you can redistribute it   
 -- and/or modify it under the terms of the GNU Lesser General   
@@ -802,14 +802,11 @@ begin
  begin
    if rising_edge(clk_sys_i) then

-      if(rst_n_i = '0') then
+      if(rst_n_i = '0') or
+        (regs_fromwb.dsr_lact_o = '1' and regs_fromwb.dsr_lact_load_o = '1') then
        regs_towb_ep.dsr_lact_i <= '0';
      else
-        if(regs_fromwb.dsr_lact_o = '1' and regs_fromwb.dsr_lact_load_o = '1') then
-          regs_towb_ep.dsr_lact_i <= '0';  -- clear-on-write
-        elsif(txpcs_fab.dvalid = '1' or rxpath_fab.dvalid = '1') then
-          regs_towb_ep.dsr_lact_i <= '1';
-        end if;
+        regs_towb_ep.dsr_lact_i <= dvalid_rx or dvalid_tx;
      end if;
    end if;
  end process;
@@ -887,7 +884,7 @@ begin
  gen_leds : if g_with_leds generate
    U_Led_Ctrl : ep_leds_controller
      generic map (
-        g_blink_period_log2 => 20)
+        g_blink_period_log2 => 22)
      port map (
        clk_sys_i   => clk_sys_i,
        rst_n_i     => rst_n_i,
@@ -899,7 +896,7 @@ begin
  end generate gen_leds;

  -------------------------- TRU stuff -----------------------------------
-  link_up_o <= link_ok;                 -- indicates that link is IP
+  link_up_o <= link_ok;                 -- indicates that link is UP

  pfilter_pclass_o <= pfilter_pclass;
  pfilter_done_o   <= pfilter_done;