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White Rabbit core collection
Commit b670fedb authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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minic: Tx path rewritten with FIFO

parent 443c0581
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Showing with 516 additions and 395 deletions
modules/wr_mini_nic/mini_nic.wb
View file @ b670fedb
......@@ -10,6 +10,13 @@ peripheral {
name = "miNIC Control Register";
prefix = "MCR";
field {
name = "TX DMA start";
prefix = "TX_START";
description = "write 1: starts the DMA transmission of TX descriptors placed in the DMA buffer, write 0: no effect";
type = MONOSTABLE;
};
field {
name = "TX DMA idle";
prefix = "TX_IDLE";
......@@ -96,10 +103,9 @@ peripheral {
name = "Data to send";
prefix = "DAT";
size = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
type = PASS_THROUGH;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
field {
......@@ -109,10 +115,9 @@ peripheral {
10: First word of a new frame";
prefix = "TYPE";
size = 2;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
type = PASS_THROUGH;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
field {
......
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ b670fedb
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wb_slave.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Tue Oct 11 10:43:48 2016
-- Created : Fri Oct 21 10:25:03 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -46,6 +46,8 @@ end minic_wb_slave;
architecture syn of minic_wb_slave is
signal minic_mcr_tx_start_dly0 : std_logic ;
signal minic_mcr_tx_start_int : std_logic ;
signal minic_mcr_rx_en_int : std_logic ;
signal minic_mcr_rx_class_int : std_logic_vector(7 downto 0);
signal minic_mprot_lo_int : std_logic_vector(15 downto 0);
......@@ -87,10 +89,11 @@ begin
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
minic_mcr_tx_start_int <= '0';
minic_mcr_rx_en_int <= '0';
minic_mcr_rx_class_int <= "00000000";
regs_o.tx_fifo_dat_load_o <= '0';
regs_o.tx_fifo_type_load_o <= '0';
regs_o.tx_fifo_dat_wr_o <= '0';
regs_o.tx_fifo_type_wr_o <= '0';
tx_ts_read_ack_o <= '0';
minic_mprot_lo_int <= "0000000000000000";
minic_mprot_hi_int <= "0000000000000000";
......@@ -103,25 +106,28 @@ begin
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.tx_fifo_dat_load_o <= '0';
regs_o.tx_fifo_type_load_o <= '0';
minic_mcr_tx_start_int <= '0';
regs_o.tx_fifo_dat_wr_o <= '0';
regs_o.tx_fifo_type_wr_o <= '0';
tx_ts_read_ack_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
regs_o.tx_fifo_dat_load_o <= '0';
regs_o.tx_fifo_type_load_o <= '0';
regs_o.tx_fifo_dat_wr_o <= '0';
regs_o.tx_fifo_type_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(4 downto 0) is
when "00000" =>
if (wb_we_i = '1') then
minic_mcr_tx_start_int <= wrdata_reg(0);
minic_mcr_rx_en_int <= wrdata_reg(10);
minic_mcr_rx_class_int <= wrdata_reg(23 downto 16);
end if;
rddata_reg(0) <= '0';
rddata_reg(1) <= regs_i.mcr_tx_idle_i;
rddata_reg(2) <= regs_i.mcr_tx_error_i;
rddata_reg(8) <= regs_i.mcr_rx_ready_i;
......@@ -130,7 +136,6 @@ begin
rddata_reg(11) <= regs_i.mcr_tx_ts_ready_i;
rddata_reg(23 downto 16) <= minic_mcr_rx_class_int;
rddata_reg(27 downto 24) <= regs_i.mcr_ver_i;
rddata_reg(0) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
......@@ -144,17 +149,33 @@ begin
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
regs_o.tx_fifo_dat_load_o <= '1';
regs_o.tx_fifo_type_load_o <= '1';
regs_o.tx_fifo_dat_wr_o <= '1';
regs_o.tx_fifo_type_wr_o <= '1';
end if;
rddata_reg(15 downto 0) <= regs_i.tx_fifo_dat_i;
rddata_reg(17 downto 16) <= regs_i.tx_fifo_type_i;
rddata_reg(30) <= regs_i.tx_fifo_empty_i;
rddata_reg(31) <= regs_i.tx_fifo_full_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
......@@ -472,6 +493,19 @@ begin
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- TX DMA start
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
minic_mcr_tx_start_dly0 <= '0';
regs_o.mcr_tx_start_o <= '0';
elsif rising_edge(clk_sys_i) then
minic_mcr_tx_start_dly0 <= minic_mcr_tx_start_int;
regs_o.mcr_tx_start_o <= minic_mcr_tx_start_int and (not minic_mcr_tx_start_dly0);
end if;
end process;
-- TX DMA idle
-- TX DMA error
-- RX DMA ready
......@@ -483,8 +517,10 @@ begin
regs_o.mcr_rx_class_o <= minic_mcr_rx_class_int;
-- Regs map version
-- Data to send
-- pass-through field: Data to send in register: TX FIFO Register
regs_o.tx_fifo_dat_o <= wrdata_reg(15 downto 0);
-- Data type
-- pass-through field: Data type in register: TX FIFO Register
regs_o.tx_fifo_type_o <= wrdata_reg(17 downto 16);
-- FIFO_EMPTY
-- FIFO_FULL
......
modules/wr_mini_nic/minic_wbgen2_pkg.vhd
View file @ b670fedb
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Tue Oct 11 10:43:48 2016
-- Created : Fri Oct 21 10:25:03 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -27,8 +27,6 @@ package minic_wbgen2_pkg is
mcr_rx_full_i : std_logic;
mcr_tx_ts_ready_i : std_logic;
mcr_ver_i : std_logic_vector(3 downto 0);
tx_fifo_dat_i : std_logic_vector(15 downto 0);
tx_fifo_type_i : std_logic_vector(1 downto 0);
tx_fifo_empty_i : std_logic;
tx_fifo_full_i : std_logic;
rx_fifo_dat_i : std_logic_vector(15 downto 0);
......@@ -50,8 +48,6 @@ package minic_wbgen2_pkg is
mcr_rx_full_i => '0',
mcr_tx_ts_ready_i => '0',
mcr_ver_i => (others => '0'),
tx_fifo_dat_i => (others => '0'),
tx_fifo_type_i => (others => '0'),
tx_fifo_empty_i => '0',
tx_fifo_full_i => '0',
rx_fifo_dat_i => (others => '0'),
......@@ -69,23 +65,25 @@ package minic_wbgen2_pkg is
-- Output registers (WB slave -> user design)
type t_minic_out_registers is record
mcr_tx_start_o : std_logic;
mcr_rx_en_o : std_logic;
mcr_rx_class_o : std_logic_vector(7 downto 0);
tx_fifo_dat_o : std_logic_vector(15 downto 0);
tx_fifo_dat_load_o : std_logic;
tx_fifo_dat_wr_o : std_logic;
tx_fifo_type_o : std_logic_vector(1 downto 0);
tx_fifo_type_load_o : std_logic;
tx_fifo_type_wr_o : std_logic;
mprot_lo_o : std_logic_vector(15 downto 0);
mprot_hi_o : std_logic_vector(15 downto 0);
end record;
constant c_minic_out_registers_init_value: t_minic_out_registers := (
mcr_tx_start_o => '0',
mcr_rx_en_o => '0',
mcr_rx_class_o => (others => '0'),
tx_fifo_dat_o => (others => '0'),
tx_fifo_dat_load_o => '0',
tx_fifo_dat_wr_o => '0',
tx_fifo_type_o => (others => '0'),
tx_fifo_type_load_o => '0',
tx_fifo_type_wr_o => '0',
mprot_lo_o => (others => '0'),
mprot_hi_o => (others => '0')
);
......@@ -124,8 +122,6 @@ tmp.mcr_rx_ready_i := f_x_to_zero(left.mcr_rx_ready_i) or f_x_to_zero(right.mcr_
tmp.mcr_rx_full_i := f_x_to_zero(left.mcr_rx_full_i) or f_x_to_zero(right.mcr_rx_full_i);
tmp.mcr_tx_ts_ready_i := f_x_to_zero(left.mcr_tx_ts_ready_i) or f_x_to_zero(right.mcr_tx_ts_ready_i);
tmp.mcr_ver_i := f_x_to_zero(left.mcr_ver_i) or f_x_to_zero(right.mcr_ver_i);
tmp.tx_fifo_dat_i := f_x_to_zero(left.tx_fifo_dat_i) or f_x_to_zero(right.tx_fifo_dat_i);
tmp.tx_fifo_type_i := f_x_to_zero(left.tx_fifo_type_i) or f_x_to_zero(right.tx_fifo_type_i);
tmp.tx_fifo_empty_i := f_x_to_zero(left.tx_fifo_empty_i) or f_x_to_zero(right.tx_fifo_empty_i);
tmp.tx_fifo_full_i := f_x_to_zero(left.tx_fifo_full_i) or f_x_to_zero(right.tx_fifo_full_i);
tmp.rx_fifo_dat_i := f_x_to_zero(left.rx_fifo_dat_i) or f_x_to_zero(right.rx_fifo_dat_i);
......
modules/wr_mini_nic/wr_mini_nic.vhd
View file @ b670fedb
This diff is collapsed.
sim/minic_regs.vh
View file @ b670fedb
......@@ -15,10 +15,28 @@
`define MINIC_MCR_TX_TS_READY 32'h00000800
`define MINIC_MCR_RX_CLASS_OFFSET 16
`define MINIC_MCR_RX_CLASS 32'h00ff0000
`define ADDR_MINIC_TX_ADDR 7'h4
`define ADDR_MINIC_RX_ADDR 7'h8
`define ADDR_MINIC_RX_SIZE 7'hc
`define ADDR_MINIC_RX_AVAIL 7'h10
`define MINIC_MCR_VER_OFFSET 24
`define MINIC_MCR_VER 32'h0f000000
`define ADDR_MINIC_TX_FIFO 7'h4
`define MINIC_TX_FIFO_DAT_OFFSET 0
`define MINIC_TX_FIFO_DAT 32'h0000ffff
`define MINIC_TX_FIFO_TYPE_OFFSET 16
`define MINIC_TX_FIFO_TYPE 32'h00030000
`define MINIC_TX_FIFO_EMPTY_OFFSET 30
`define MINIC_TX_FIFO_EMPTY 32'h40000000
`define MINIC_TX_FIFO_FULL_OFFSET 31
`define MINIC_TX_FIFO_FULL 32'h80000000
`define ADDR_MINIC_RX_FIFO 7'h8
`define MINIC_RX_FIFO_DAT_OFFSET 0
`define MINIC_RX_FIFO_DAT 32'h0000ffff
`define MINIC_RX_FIFO_TYPE_OFFSET 16
`define MINIC_RX_FIFO_TYPE 32'h00030000
`define MINIC_RX_FIFO_EMPTY_OFFSET 30
`define MINIC_RX_FIFO_EMPTY 32'h40000000
`define MINIC_RX_FIFO_FULL_OFFSET 31
`define MINIC_RX_FIFO_FULL 32'h80000000
`define ADDR_MINIC_RESV_1 7'hc
`define ADDR_MINIC_RESV_2 7'h10
`define ADDR_MINIC_TSR0 7'h14
`define MINIC_TSR0_VALID_OFFSET 0
`define MINIC_TSR0_VALID 32'h00000001
......
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