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White Rabbit core collection
Commit 10ccc8c1 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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update testbeches Manifests to use new hdlmake

parent 486137e9
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Showing with 69 additions and 10 deletions
testbench/top_level/Manifest.py
View file @ 10ccc8c1
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
include_dirs = [ "../../sim", "gn4124_bfm" ]
files = [ "main.sv" ]
modules = { "local" : [ "../..",
......
testbench/wr_endpoint/full_tb/Manifest.py
View file @ 10ccc8c1
target = "xilinx"
action = "simulation"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
files = "main.sv"
fetchto = "../../../ip_cores"
vlog_opt="+incdir+../../../sim +incdir+../../../sim/fabric_emu"
include_dirs = [ "../../../sim" ]
modules ={"git" : [ "git@ohwr.org:hdl-core-lib/general-cores.git" ],
"local" : ["../../../modules/wr_endpoint",
"../../../modules/timing",
......
testbench/wr_fabric_reg/Manifest.py 0 → 100644
View file @ 10ccc8c1
action = "simulation"
files = "main.sv"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../ip_cores"
target = "xilinx"
vlog_opt="+incdir+../../sim"
include_dirs = [ "../../sim" ]
modules ={"local" : ["../../",
"../../ip_cores/general-cores",
"../../ip_cores/etherbone-core",
"../../ip_cores/gn4124-core"]}
testbench/wr_minic/Manifest.py
View file @ 10ccc8c1
action = "simulation"
target = "xilinx"
#syn_device = "xc6slx45t"
#syn_grade = "-3"
#syn_package = "fgg484"
#sim_tool = "modelsim"
#top_module = "main"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim"
include_dirs = [ "../../sim" ]
files = [ "main.sv" ]
modules = { "local" : [ "../../",
......
testbench/wrc_core/main_tb/Manifest.py
View file @ 10ccc8c1
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../../ip_cores"
vlog_opt = "+incdir+../../../sim"
files = [ "main.sv" ]
include_dirs = [ "../../../sim" ]
modules = { "local" : [ "../../..",
"../../../modules/fabric",
"../../../ip_cores/general-cores",
"../../../ip_cores/etherbone-core",
"../../../ip_cores/gn4124-core"]}
"../../../ip_cores/gn4124-core",
"../../../ip_cores/urv-core" ]}
testbench/xwrf_loopback/Manifest.py
View file @ 10ccc8c1
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim"
include_dirs = [ "../../sim" ]
files = [ "main.sv" ]
modules = { "local" : [ "../..",
......
testbench/xwrf_mux/Manifest.py
View file @ 10ccc8c1
action = "simulation"
target = "xilinx"
files = "main.sv"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../ip_cores"
target = "xilinx"
vlog_opt="+incdir+../../sim"
modules ={"local" : "../../" }
include_dirs = [ "../../sim" ]
modules ={"local" : ["../../",
"../../ip_cores/general-cores",
"../../ip_cores/etherbone-core",
"../../ip_cores/gn4124-core"]}
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