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White Rabbit core collection
Commit 7d17ce87 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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Merge branch 'minic_fifo' into proposed_master

parents bad54c60 934eb7ff
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Showing with 26128 additions and 23189 deletions
.gitignore
View file @ 7d17ce87
......@@ -15,4 +15,5 @@ doc/
*.o
*.bin
*.elf
*.ucdb
Makefile
general-cores @ 0d75c0fd
Subproject commit 4f216443aea2e4a50223c7b72cd02bbbef5bf7c9
Subproject commit 0d75c0fdc0059b9ce3a8adb76a4ff14b5b795d6c
modules/wr_mini_nic/build_wb.sh
View file @ 7d17ce87
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/minic.html -V minic_wb_slave.vhd -p minic_wbgen2_pkg.vhd --cstyle defines --lang vhdl -H record -K ../../sim/minic_regs.vh mini_nic.wb
\ No newline at end of file
wbgen2 -D ./doc/minic.html -C minic_regs.h -V minic_wb_slave.vhd -p minic_wbgen2_pkg.vhd --cstyle defines --lang vhdl -H record -K ../../sim/minic_regs.vh mini_nic.wb
modules/wr_mini_nic/mini_nic.wb
View file @ 7d17ce87
......@@ -6,7 +6,7 @@ peripheral {
prefix = "minic";
hdl_entity = "minic_wb_slave";
reg {
reg {
name = "miNIC Control Register";
prefix = "MCR";
......@@ -22,6 +22,7 @@ peripheral {
prefix = "TX_IDLE";
description = "1: TX DMA engine is idle.\n0: TX DMA engine is busy, don't touch the buffer";
type = BIT;
align = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
......@@ -36,119 +37,189 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "RX DMA ready";
prefix = "RX_READY";
description = "1: RX buffer contains at least one packet";
type = BIT;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
field {
name = "TX_FIFO_EMPTY";
prefix = "TX_EMPTY";
size = 1;
align = 3;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX_FIFO_FULL";
prefix = "TX_FULL";
size = 1;
align = 4;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX DMA ready";
prefix = "RX_READY";
description = "1: RX buffer contains at least one packet";
type = BIT;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX DMA buffer full";
prefix = "RX_FULL";
description = "1: RX buffer is full";
name = "RX DMA error";
prefix = "RX_ERROR";
description = "1: RX error, FIFO overflow";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX DMA enable";
prefix = "RX_EN";
description = "1: RX buffer is allocated and initialized by the host, the miNIC can receive packets\n0: RX buffer not ready, reception is disabled";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "RX DMA enable";
prefix = "RX_EN";
description = "1: RX buffer is allocated and initialized by the host, the miNIC can receive packets\n0: RX buffer not ready, reception is disabled";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "TX TS ready";
prefix = "TX_TS_READY";
description = "1: the TX transfer is complete and a timestamp is available";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX TS ready";
prefix = "TX_TS_READY";
description = "1: the TX transfer is complete and a timestamp is available";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX Accepted Packet Classes";
prefix = "RX_CLASS";
size = 8;
align = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX DMA Address";
description = "Address of the start of TX buffer:\
read: base address of the last transmitted TX descriptor\
write: base address of the first descriptor to transmit";
prefix = "TX_ADDR";
field {
name = "TX DMA buffer address";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
field {
name = "RX_FIFO_EMPTY";
prefix = "RX_EMPTY";
size = 1;
align = 12;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX_FIFO_FULL";
prefix = "RX_FULL";
size = 1;
align = 13;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
reg {
name = "RX DMA Address";
description = "Address of the start of RX buffer:\
read: address of the last received RX descriptor\
write: base address of the RX buffer";
prefix = "RX_ADDR";
field {
name = "RX DMA buffer address";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
field {
name = "RX Accepted Packet Classes";
prefix = "RX_CLASS";
size = 8;
align = 16;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
reg {
name = "RX buffer size register";
description = "Size of RX buffer in 32-bit words";
prefix = "RX_SIZE";
field {
name = "RX available words";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
field {
name = "Regs map version";
prefix = "VER";
size = 4;
align = 24;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "TX FIFO Register";
prefix = "TX_FIFO";
reg {
name = "RX buffer available words register";
description = "Number of available 32-bit words in the RX buffer\
read: available words in RX buffer\
write: increment available words in RX buffer";
prefix = "RX_AVAIL";
field {
name = "RX available words";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
field {
name = "Data to send";
prefix = "DAT";
size = 16;
type = PASS_THROUGH;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
field {
name = "Data type";
description = "00: normal data\
01: OOB data\
10: First word of a new frame";
prefix = "TYPE";
size = 2;
type = PASS_THROUGH;
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
};
reg {
name = "RX FIFO Register";
prefix = "RX_FIFO";
field {
name = "Data to send";
prefix = "DAT";
size = 16;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Data type";
description = "00: normal data\
01: OOB data\
10: First word of a new frame";
prefix = "TYPE";
size = 2;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX_FIFO_EMPTY";
prefix = "EMPTY";
size = 1;
align = 30;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX_FIFO_FULL";
prefix = "FULL";
size = 1;
align = 31;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "reserved 1";
prefix = "RESV_1";
};
reg {
name = "reserved 2";
prefix = "RESV_2";
};
reg {
name = "TX timestamp register 0";
......
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ 7d17ce87
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wb_slave.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Thu Aug 6 16:03:26 2015
-- Created : Wed Oct 26 11:30:27 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -92,10 +92,8 @@ begin
minic_mcr_tx_start_int <= '0';
minic_mcr_rx_en_int <= '0';
minic_mcr_rx_class_int <= "00000000";
regs_o.tx_addr_load_o <= '0';
regs_o.rx_addr_load_o <= '0';
regs_o.rx_size_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
regs_o.tx_fifo_dat_wr_o <= '0';
regs_o.tx_fifo_type_wr_o <= '0';
tx_ts_read_ack_o <= '0';
minic_mprot_lo_int <= "0000000000000000";
minic_mprot_hi_int <= "0000000000000000";
......@@ -109,20 +107,16 @@ begin
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
minic_mcr_tx_start_int <= '0';
regs_o.tx_addr_load_o <= '0';
regs_o.rx_addr_load_o <= '0';
regs_o.rx_size_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
regs_o.tx_fifo_dat_wr_o <= '0';
regs_o.tx_fifo_type_wr_o <= '0';
tx_ts_read_ack_o <= '0';
eic_idr_write_int <= '0';
eic_ier_write_int <= '0';
eic_isr_write_int <= '0';
ack_in_progress <= '0';
else
regs_o.tx_addr_load_o <= '0';
regs_o.rx_addr_load_o <= '0';
regs_o.rx_size_load_o <= '0';
regs_o.rx_avail_load_o <= '0';
regs_o.tx_fifo_dat_wr_o <= '0';
regs_o.tx_fifo_type_wr_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
......@@ -136,24 +130,21 @@ begin
rddata_reg(0) <= '0';
rddata_reg(1) <= regs_i.mcr_tx_idle_i;
rddata_reg(2) <= regs_i.mcr_tx_error_i;
rddata_reg(3) <= regs_i.mcr_tx_empty_i;
rddata_reg(4) <= regs_i.mcr_tx_full_i;
rddata_reg(8) <= regs_i.mcr_rx_ready_i;
rddata_reg(9) <= regs_i.mcr_rx_full_i;
rddata_reg(9) <= regs_i.mcr_rx_error_i;
rddata_reg(10) <= minic_mcr_rx_en_int;
rddata_reg(11) <= regs_i.mcr_tx_ts_ready_i;
rddata_reg(12) <= regs_i.mcr_rx_empty_i;
rddata_reg(13) <= regs_i.mcr_rx_full_i;
rddata_reg(23 downto 16) <= minic_mcr_rx_class_int;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(27 downto 24) <= regs_i.mcr_ver_i;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
......@@ -162,9 +153,33 @@ begin
ack_in_progress <= '1';
when "00001" =>
if (wb_we_i = '1') then
regs_o.tx_addr_load_o <= '1';
regs_o.tx_fifo_dat_wr_o <= '1';
regs_o.tx_fifo_type_wr_o <= '1';
end if;
rddata_reg(23 downto 0) <= regs_i.tx_addr_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -177,24 +192,52 @@ begin
ack_in_progress <= '1';
when "00010" =>
if (wb_we_i = '1') then
regs_o.rx_addr_load_o <= '1';
end if;
rddata_reg(23 downto 0) <= regs_i.rx_addr_i;
rddata_reg(15 downto 0) <= regs_i.rx_fifo_dat_i;
rddata_reg(17 downto 16) <= regs_i.rx_fifo_type_i;
rddata_reg(30) <= regs_i.rx_fifo_empty_i;
rddata_reg(31) <= regs_i.rx_fifo_full_i;
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00011" =>
if (wb_we_i = '1') then
regs_o.rx_size_load_o <= '1';
end if;
rddata_reg(23 downto 0) <= regs_i.rx_size_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -207,9 +250,31 @@ begin
ack_in_progress <= '1';
when "00100" =>
if (wb_we_i = '1') then
regs_o.rx_avail_load_o <= '1';
end if;
rddata_reg(23 downto 0) <= regs_i.rx_avail_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
......@@ -443,21 +508,28 @@ begin
-- TX DMA idle
-- TX DMA error
-- TX_FIFO_EMPTY
-- TX_FIFO_FULL
-- RX DMA ready
-- RX DMA buffer full
-- RX DMA error
-- RX DMA enable
regs_o.mcr_rx_en_o <= minic_mcr_rx_en_int;
-- TX TS ready
-- RX_FIFO_EMPTY
-- RX_FIFO_FULL
-- RX Accepted Packet Classes
regs_o.mcr_rx_class_o <= minic_mcr_rx_class_int;
-- TX DMA buffer address
regs_o.tx_addr_o <= wrdata_reg(23 downto 0);
-- RX DMA buffer address
regs_o.rx_addr_o <= wrdata_reg(23 downto 0);
-- RX available words
regs_o.rx_size_o <= wrdata_reg(23 downto 0);
-- RX available words
regs_o.rx_avail_o <= wrdata_reg(23 downto 0);
-- Regs map version
-- Data to send
-- pass-through field: Data to send in register: TX FIFO Register
regs_o.tx_fifo_dat_o <= wrdata_reg(15 downto 0);
-- Data type
-- pass-through field: Data type in register: TX FIFO Register
regs_o.tx_fifo_type_o <= wrdata_reg(17 downto 16);
-- Data to send
-- Data type
-- RX_FIFO_EMPTY
-- RX_FIFO_FULL
-- Timestamp valid
-- Port ID
-- Frame ID
......
modules/wr_mini_nic/minic_wbgen2_pkg.vhd
View file @ 7d17ce87
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Thu Aug 6 16:03:26 2015
-- Created : Wed Oct 26 11:30:27 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -23,13 +23,18 @@ package minic_wbgen2_pkg is
type t_minic_in_registers is record
mcr_tx_idle_i : std_logic;
mcr_tx_error_i : std_logic;
mcr_tx_empty_i : std_logic;
mcr_tx_full_i : std_logic;
mcr_rx_ready_i : std_logic;
mcr_rx_full_i : std_logic;
mcr_rx_error_i : std_logic;
mcr_tx_ts_ready_i : std_logic;
tx_addr_i : std_logic_vector(23 downto 0);
rx_addr_i : std_logic_vector(23 downto 0);
rx_size_i : std_logic_vector(23 downto 0);
rx_avail_i : std_logic_vector(23 downto 0);
mcr_rx_empty_i : std_logic;
mcr_rx_full_i : std_logic;
mcr_ver_i : std_logic_vector(3 downto 0);
rx_fifo_dat_i : std_logic_vector(15 downto 0);
rx_fifo_type_i : std_logic_vector(1 downto 0);
rx_fifo_empty_i : std_logic;
rx_fifo_full_i : std_logic;
tsr0_valid_i : std_logic;
tsr0_pid_i : std_logic_vector(4 downto 0);
tsr0_fid_i : std_logic_vector(15 downto 0);
......@@ -41,13 +46,18 @@ package minic_wbgen2_pkg is
constant c_minic_in_registers_init_value: t_minic_in_registers := (
mcr_tx_idle_i => '0',
mcr_tx_error_i => '0',
mcr_tx_empty_i => '0',
mcr_tx_full_i => '0',
mcr_rx_ready_i => '0',
mcr_rx_full_i => '0',
mcr_rx_error_i => '0',
mcr_tx_ts_ready_i => '0',
tx_addr_i => (others => '0'),
rx_addr_i => (others => '0'),
rx_size_i => (others => '0'),
rx_avail_i => (others => '0'),
mcr_rx_empty_i => '0',
mcr_rx_full_i => '0',
mcr_ver_i => (others => '0'),
rx_fifo_dat_i => (others => '0'),
rx_fifo_type_i => (others => '0'),
rx_fifo_empty_i => '0',
rx_fifo_full_i => '0',
tsr0_valid_i => '0',
tsr0_pid_i => (others => '0'),
tsr0_fid_i => (others => '0'),
......@@ -62,14 +72,10 @@ package minic_wbgen2_pkg is
mcr_tx_start_o : std_logic;
mcr_rx_en_o : std_logic;
mcr_rx_class_o : std_logic_vector(7 downto 0);
tx_addr_o : std_logic_vector(23 downto 0);
tx_addr_load_o : std_logic;
rx_addr_o : std_logic_vector(23 downto 0);
rx_addr_load_o : std_logic;
rx_size_o : std_logic_vector(23 downto 0);
rx_size_load_o : std_logic;
rx_avail_o : std_logic_vector(23 downto 0);
rx_avail_load_o : std_logic;
tx_fifo_dat_o : std_logic_vector(15 downto 0);
tx_fifo_dat_wr_o : std_logic;
tx_fifo_type_o : std_logic_vector(1 downto 0);
tx_fifo_type_wr_o : std_logic;
mprot_lo_o : std_logic_vector(15 downto 0);
mprot_hi_o : std_logic_vector(15 downto 0);
end record;
......@@ -78,14 +84,10 @@ package minic_wbgen2_pkg is
mcr_tx_start_o => '0',
mcr_rx_en_o => '0',
mcr_rx_class_o => (others => '0'),
tx_addr_o => (others => '0'),
tx_addr_load_o => '0',
rx_addr_o => (others => '0'),
rx_addr_load_o => '0',
rx_size_o => (others => '0'),
rx_size_load_o => '0',
rx_avail_o => (others => '0'),
rx_avail_load_o => '0',
tx_fifo_dat_o => (others => '0'),
tx_fifo_dat_wr_o => '0',
tx_fifo_type_o => (others => '0'),
tx_fifo_type_wr_o => '0',
mprot_lo_o => (others => '0'),
mprot_hi_o => (others => '0')
);
......@@ -120,13 +122,18 @@ variable tmp: t_minic_in_registers;
begin
tmp.mcr_tx_idle_i := f_x_to_zero(left.mcr_tx_idle_i) or f_x_to_zero(right.mcr_tx_idle_i);
tmp.mcr_tx_error_i := f_x_to_zero(left.mcr_tx_error_i) or f_x_to_zero(right.mcr_tx_error_i);
tmp.mcr_tx_empty_i := f_x_to_zero(left.mcr_tx_empty_i) or f_x_to_zero(right.mcr_tx_empty_i);
tmp.mcr_tx_full_i := f_x_to_zero(left.mcr_tx_full_i) or f_x_to_zero(right.mcr_tx_full_i);
tmp.mcr_rx_ready_i := f_x_to_zero(left.mcr_rx_ready_i) or f_x_to_zero(right.mcr_rx_ready_i);
tmp.mcr_rx_full_i := f_x_to_zero(left.mcr_rx_full_i) or f_x_to_zero(right.mcr_rx_full_i);
tmp.mcr_rx_error_i := f_x_to_zero(left.mcr_rx_error_i) or f_x_to_zero(right.mcr_rx_error_i);
tmp.mcr_tx_ts_ready_i := f_x_to_zero(left.mcr_tx_ts_ready_i) or f_x_to_zero(right.mcr_tx_ts_ready_i);
tmp.tx_addr_i := f_x_to_zero(left.tx_addr_i) or f_x_to_zero(right.tx_addr_i);
tmp.rx_addr_i := f_x_to_zero(left.rx_addr_i) or f_x_to_zero(right.rx_addr_i);
tmp.rx_size_i := f_x_to_zero(left.rx_size_i) or f_x_to_zero(right.rx_size_i);
tmp.rx_avail_i := f_x_to_zero(left.rx_avail_i) or f_x_to_zero(right.rx_avail_i);
tmp.mcr_rx_empty_i := f_x_to_zero(left.mcr_rx_empty_i) or f_x_to_zero(right.mcr_rx_empty_i);
tmp.mcr_rx_full_i := f_x_to_zero(left.mcr_rx_full_i) or f_x_to_zero(right.mcr_rx_full_i);
tmp.mcr_ver_i := f_x_to_zero(left.mcr_ver_i) or f_x_to_zero(right.mcr_ver_i);
tmp.rx_fifo_dat_i := f_x_to_zero(left.rx_fifo_dat_i) or f_x_to_zero(right.rx_fifo_dat_i);
tmp.rx_fifo_type_i := f_x_to_zero(left.rx_fifo_type_i) or f_x_to_zero(right.rx_fifo_type_i);
tmp.rx_fifo_empty_i := f_x_to_zero(left.rx_fifo_empty_i) or f_x_to_zero(right.rx_fifo_empty_i);
tmp.rx_fifo_full_i := f_x_to_zero(left.rx_fifo_full_i) or f_x_to_zero(right.rx_fifo_full_i);
tmp.tsr0_valid_i := f_x_to_zero(left.tsr0_valid_i) or f_x_to_zero(right.tsr0_valid_i);
tmp.tsr0_pid_i := f_x_to_zero(left.tsr0_pid_i) or f_x_to_zero(right.tsr0_pid_i);
tmp.tsr0_fid_i := f_x_to_zero(left.tsr0_fid_i) or f_x_to_zero(right.tsr0_fid_i);
......
modules/wr_mini_nic/wr_mini_nic.vhd
View file @ 7d17ce87
This diff is collapsed.
modules/wr_mini_nic/xwr_mini_nic.vhd
View file @ 7d17ce87
......@@ -9,22 +9,14 @@ entity xwr_mini_nic is
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_memsize_log2 : integer := 14;
g_tx_fifo_size : integer := 1024;
g_rx_fifo_size : integer := 2048;
g_buffer_little_endian : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-------------------------------------------------------------------------------
-- System memory i/f
-------------------------------------------------------------------------------
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
-------------------------------------------------------------------------------
-- Pipelined Wishbone interface
-------------------------------------------------------------------------------
......@@ -63,15 +55,12 @@ architecture wrapper of xwr_mini_nic is
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_memsize_log2 : integer;
g_tx_fifo_size : integer;
g_rx_fifo_size : integer;
g_buffer_little_endian : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
src_dat_o : out std_logic_vector(15 downto 0);
src_adr_o : out std_logic_vector(1 downto 0);
src_sel_o : out std_logic_vector(1 downto 0);
......@@ -114,15 +103,12 @@ begin -- wrapper
generic map (
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_memsize_log2 => g_memsize_log2,
g_tx_fifo_size => g_tx_fifo_size,
g_rx_fifo_size => g_rx_fifo_size,
g_buffer_little_endian => g_buffer_little_endian)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
mem_data_o => mem_data_o,
mem_addr_o => mem_addr_o,
mem_data_i => mem_data_i,
mem_wr_o => mem_wr_o,
src_dat_o => src_o.dat,
src_adr_o => src_o.adr,
src_sel_o => src_o.sel,
......
modules/wrc_core/wr_core.vhd
View file @ 7d17ce87
This diff is collapsed.
modules/wrc_core/wrcore_pkg.vhd
View file @ 7d17ce87
......@@ -83,15 +83,12 @@ package wrcore_pkg is
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_memsize_log2 : integer;
g_tx_fifo_size : integer;
g_rx_fifo_size : integer;
g_buffer_little_endian : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
mem_data_o : out std_logic_vector(31 downto 0);
mem_addr_o : out std_logic_vector(g_memsize_log2-1 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_wr_o : out std_logic;
src_o : out t_wrf_source_out;
src_i : in t_wrf_source_in;
snk_o : out t_wrf_sink_out;
......
sim/drivers/simdrv_minic.svh
View file @ 7d17ce87
......@@ -14,14 +14,19 @@ class CSimDrv_Minic;
`define RX_DESC_ERROR(d) ((d) & (1<<30) ? 1 : 0)
`define RX_DESC_HAS_OOB(d) ((d) & (1<<29) ? 1 : 0)
`define RX_DESC_SIZE(d) (((d) & (1<<0) ? -1 : 0) + (d & 'hffe))
`define c_WRF_DATA 0
`define c_WRF_OOB 1
`define c_WRF_STATUS 2
`define c_WRF_BYTESEL 3
protected CBusAccessor acc_regs, acc_pmem;
protected uint32_t base_regs, base_pmem;
protected int pmem_size;
protected bit little_endian;
protected uint32_t tx_head, tx_base, tx_avail, tx_size, tx_count, tx_oob_val;
protected uint32_t rx_head, rx_base, rx_avail, rx_size, rx_count;
protected uint32_t tx_head, tx_base, tx_avail, tx_size, tx_oob_val;
protected uint32_t rx_head, rx_base, rx_avail, rx_size;
protected EthPacket rx_queue[$];
......@@ -29,93 +34,110 @@ class CSimDrv_Minic;
const int MINIC_MTU = 1536;
function new(int pmem_size_, CBusAccessor regs_, uint32_t base_regs_, CBusAccessor pmem_, uint32_t base_pmem_);
base_pmem = base_pmem_;
function new(CBusAccessor regs_, uint32_t base_regs_);
base_regs = base_regs_;
acc_regs = regs_;
acc_pmem = pmem_;
pmem_size = pmem_size_;
little_endian = 1;
endfunction // new
little_endian = 0;
endfunction
task minic_writel(uint32_t addr, uint32_t val);
acc_regs.write(base_regs + addr, val, 4);
endtask // minic_writel
endtask
task minic_readl(uint32_t addr, output uint32_t val);
uint64_t tmp;
acc_regs.read(base_regs + addr, tmp, 4);
val = tmp;
endtask // minic_writel
endtask
task minic_write_txword(uint32_t word_type, uint32_t word);
uint32_t val;
val = word_type << `MINIC_TX_FIFO_TYPE_OFFSET;
val = val | (word & `MINIC_TX_FIFO_DAT);
minic_writel(`ADDR_MINIC_TX_FIFO, val);
endtask
task new_tx_buffer();
tx_head = tx_base;
tx_avail = (tx_size - MINIC_MTU) >> 2;
minic_writel(`ADDR_MINIC_TX_ADDR, tx_base);
endtask // new_tx_buffers
task new_rx_buffer();
rx_head = rx_base;
minic_writel(`ADDR_MINIC_MCR, 0);
minic_writel(`ADDR_MINIC_RX_ADDR, rx_base);
minic_writel(`ADDR_MINIC_RX_SIZE, rx_size >> 2);
minic_writel(`ADDR_MINIC_EIC_ISR, `MINIC_EIC_ISR_RX);
minic_writel(`ADDR_MINIC_MCR, `MINIC_MCR_RX_EN);
endtask // new_rx_buffer
//task new_tx_buffer();
// tx_head = tx_base;
// tx_avail = (tx_size - MINIC_MTU) >> 2;
// minic_writel(`ADDR_MINIC_TX_ADDR, tx_base);
//endtask // new_tx_buffers
//task new_rx_buffer();
// rx_head = rx_base;
// minic_writel(`ADDR_MINIC_MCR, 0);
// minic_writel(`ADDR_MINIC_RX_ADDR, rx_base);
// minic_writel(`ADDR_MINIC_RX_SIZE, rx_size >> 2);
// minic_writel(`ADDR_MINIC_EIC_ISR, `MINIC_EIC_ISR_RX);
// minic_writel(`ADDR_MINIC_MCR, `MINIC_MCR_RX_EN);
//endtask // new_rx_buffer
task init();
uint32_t lo, hi;
uint32_t val;
minic_writel(`ADDR_MINIC_EIC_IDR, `MINIC_EIC_IDR_RX);
minic_writel(`ADDR_MINIC_EIC_ISR, `MINIC_EIC_ISR_RX);
tx_base = base_pmem;
tx_size = pmem_size / 2;
rx_base = base_pmem + pmem_size / 2;
rx_size = pmem_size / 2;
//tx_base = base_pmem;
//tx_size = pmem_size / 2;
//rx_base = base_pmem + pmem_size / 2;
//rx_size = pmem_size / 2;
tx_oob_val = 12345;
//enable RX
minic_readl(`ADDR_MINIC_MCR, val);
minic_writel(`ADDR_MINIC_MCR, val | `MINIC_MCR_RX_EN);
lo = rx_base >> 2;
hi = (rx_base >> 2) + (rx_size >> 2) - 1;
minic_writel(`ADDR_MINIC_MPROT, (lo << `MINIC_MPROT_LO_OFFSET) | (hi << `MINIC_MPROT_HI_OFFSET));
tx_count = 0;
rx_count = 0;
new_rx_buffer();
minic_writel(`ADDR_MINIC_EIC_IER, `MINIC_EIC_IER_RX);
endtask // init
task tx_frame(byte payload[], uint32_t size, bit with_oob, int ts_id, output uint32_t ts, output int port_id);
task tx_frame(byte frame[], uint32_t size, bit with_oob, int frame_id, output uint32_t ts, output int port_id);
int i;
uint32_t d_hdr, mcr, nwords;
uint32_t size_words;
uint16_t word;
u64_array_t buff;
int bytesel = 0;
byte tmp[];
byte oob[2];
new_tx_buffer();
//new_tx_buffer();
$display("Minic TX frame(%d): size=%d, with_oob=%d", frame_id, size, with_oob);
if(size < 60) size = 60;
if(size & 1) size = size + 1;
if(size & 1) begin
size = size + 1;
bytesel = 1;
end
tmp = new[size](payload);
//tmp = new[size](payload);
buff = SimUtils.pack({0,0,0,0, tmp, 0,0,0,0}, 4, 1);
size = size / 2;
for(i=0;i<buff.size(); i++)
acc_pmem.write(tx_head + i*4, buff[i], 4);
//buff = SimUtils.pack({0,0,0,0, tmp, 0,0,0,0}, 4, 1);
size_words = size / 2;
//first we write status word (empty status)
minic_write_txword(`c_WRF_STATUS, 0);
acc_pmem.write(tx_head, TX_DESC_HAS_OWN_MAC | TX_DESC_VALID | (with_oob ? TX_DESC_WITH_OOB :0 )| size | (ts_id << 12), 4);
//then we write the actual frame
for(i=0;i<size_words-1; i++) begin
word = (frame[2*i] << 8) | (frame[2*i+1] & 'h00FF);
minic_write_txword(`c_WRF_DATA, word);
end
//write the last word with bytesel or normal
if(bytesel == 1)
minic_write_txword(`c_WRF_BYTESEL, frame[2*i] << 8);
else begin
word = (frame[2*i] << 8) | (frame[2*i+1] & 'h00FF);
minic_write_txword(`c_WRF_DATA, word);
end
if (with_oob) begin
minic_write_txword(`c_WRF_OOB, 'h1000);
minic_write_txword(`c_WRF_OOB, frame_id);
end
minic_readl(`ADDR_MINIC_MCR, mcr);
minic_writel(`ADDR_MINIC_MCR, mcr | `MINIC_MCR_TX_START);
......@@ -128,69 +150,66 @@ class CSimDrv_Minic;
uint32_t raw_ts;
uint32_t rx_addr_cur, mcr, cur_avail;
u64_array_t pbuff;
uint32_t val;
uint32_t typ, data;
byte tmp_payload[2000];
int i;
int n_recvd;
int done;
uint32_t isr;
minic_readl(`ADDR_MINIC_EIC_ISR, isr);
if(! (isr & `MINIC_EIC_ISR_RX))
return;
acc_pmem.read(rx_head, desc_hdr);
if(!`RX_DESC_VALID(desc_hdr))
begin
$error("SimDRV_Minic::rx_frame: weird, invalid RX desc header");
$stop;
//minic_readl(`ADDR_MINIC_EIC_ISR, isr);
//
//if(! (isr & `MINIC_EIC_ISR_RX))
// return;
// if RX FIFO is empty, quit immediatelly
minic_readl(`ADDR_MINIC_MCR, val);
if ( val & `MINIC_MCR_RX_EMPTY )
return ;
size = 0;
done = 0;
// get frame from FIFO
do begin
minic_readl(`ADDR_MINIC_RX_FIFO, val);
typ = (val & `MINIC_RX_FIFO_TYPE) >> `MINIC_RX_FIFO_TYPE_OFFSET;
data = (val & `MINIC_RX_FIFO_DAT);
if (typ == `c_WRF_DATA) begin
tmp_payload[size] = data >> 8;
tmp_payload[size+1] = data & 'h00FF;
size = size + 2;
end
payload_size = `RX_DESC_SIZE(desc_hdr);
num_words = (payload_size + 3) >> 2;
pbuff = new [num_words];
// $display("NWords %d hdr %x", num_words, desc_hdr);
if(`RX_DESC_HAS_OOB(desc_hdr))
payload_size = payload_size - 6;
if(!`RX_DESC_ERROR(desc_hdr))
begin
for(i=0; i<num_words;i++)
acc_pmem.read((rx_head + 4 + i * 4) % rx_size, pbuff[i]);
payload = SimUtils.unpack(pbuff, 4, payload_size);
else if (typ == `c_WRF_BYTESEL) begin
tmp_payload[size] = data >> 8;
size = size + 1;
end
else if (typ == `c_WRF_STATUS && size != 0) begin
// which means we got status for next frame
done = 1;
end
size = payload_size;
rx_head = (rx_head + 4 + num_words * 4 - rx_base) % rx_size + rx_base;
minic_writel(`ADDR_MINIC_RX_AVAIL, (num_words + 1));
minic_readl(`ADDR_MINIC_RX_AVAIL, cur_avail);
end while ( !(val & `MINIC_RX_FIFO_EMPTY) && typ != `c_WRF_OOB && done == 0);
acc_pmem.read(rx_head, desc_hdr);
payload = new[size](tmp_payload);
if( cur_avail == (rx_size>>2) || !(`RX_DESC_VALID(desc_hdr)))
begin
minic_readl(`ADDR_MINIC_MCR, mcr);
if(mcr & `MINIC_MCR_RX_FULL)
new_rx_buffer();
if (typ != `c_WRF_OOB)
$display("!! Incomplete frame");
minic_writel(`ADDR_MINIC_EIC_ISR, `MINIC_EIC_ISR_RX);
end
// now let's see if the frame has OOB
while (typ == `c_WRF_OOB && !(val & `MINIC_RX_FIFO_EMPTY)) begin
minic_readl(`ADDR_MINIC_RX_FIFO, val);
typ = (val & `MINIC_RX_FIFO_TYPE) >> `MINIC_RX_FIFO_TYPE_OFFSET;
data = (val & `MINIC_RX_FIFO_DAT);
end
endtask // rx_frame
task do_rx();
byte payload[];
uint32_t size, ts;
uint32_t size, psize, ts;
bit with_ts;
rx_frame(payload, size, with_ts, ts);
......@@ -198,8 +217,15 @@ class CSimDrv_Minic;
if(payload.size() > 0)
begin
EthPacket pkt;
int id;
psize = 0;
if (payload.size() > 14) begin
psize = payload.size() - 14; //14 for the header
end
pkt = new;
pkt.deserialize(payload);
id = ((pkt.payload[1] << 8) & 'hff00) | pkt.payload[0];
$display("Minic RX frame(%d): size %d (%d)", id, psize, payload.size());
rx_queue.push_back(pkt);
end
......
sim/eth_packet.svh
View file @ 7d17ce87
......@@ -64,7 +64,7 @@ class EthPacket;
is_hp = 0;
has_crc = 0;
oob_type = NONE;
payload = new[size](payload);
payload = new[size](payload);
endfunction // new
......@@ -180,6 +180,10 @@ class EthPacket;
if(oob_type == TX_FID && (b.ts.frame_id != ts.frame_id))
return 0;
if(oob_type == RX_TIMESTAMP && (b.ts.ts_r != ts.ts_r) && (b.ts.ts_f !=
ts.ts_f))
return 0;
end
return 1;
......@@ -233,6 +237,10 @@ is_hp ? "H" : " ", has_crc ? "C" : " ");
$sformat(tmp, "TxOOB: %x", ts.frame_id);
str = {str, tmp};
end
if(oob_type == RX_TIMESTAMP) begin
$sformat(tmp, "RxOOB: %x, %x", ts.ts_f, ts.ts_r);
str = {str, tmp};
end
$display(str);
hexdump(payload);
......@@ -264,6 +272,7 @@ class EthPacketGenerator;
protected int r_flags;
protected int m_current_frame_id;
protected int current_ts;
protected int cur_seq_id;
function new();
......@@ -271,6 +280,7 @@ class EthPacketGenerator;
min_size = 64;
max_size = 128;
m_current_frame_id = 0;
current_ts = 0;
template = new;
cur_seq_id = 0;
......@@ -361,6 +371,13 @@ class EthPacketGenerator;
pkt.oob_type = TX_FID;
end
if(r_flags & RX_OOB) begin
pkt.oob_type = RX_TIMESTAMP;
pkt.ts.port_id = 0;
pkt.ts.ts_r = ++current_ts;
pkt.ts.ts_f = current_ts;
end
pkt.size = len + 14; //payload + header
return pkt;
......
sim/minic_regs.vh
View file @ 7d17ce87
......@@ -5,20 +5,42 @@
`define MINIC_MCR_TX_IDLE 32'h00000002
`define MINIC_MCR_TX_ERROR_OFFSET 2
`define MINIC_MCR_TX_ERROR 32'h00000004
`define MINIC_MCR_TX_EMPTY_OFFSET 3
`define MINIC_MCR_TX_EMPTY 32'h00000008
`define MINIC_MCR_TX_FULL_OFFSET 4
`define MINIC_MCR_TX_FULL 32'h00000010
`define MINIC_MCR_RX_READY_OFFSET 8
`define MINIC_MCR_RX_READY 32'h00000100
`define MINIC_MCR_RX_FULL_OFFSET 9
`define MINIC_MCR_RX_FULL 32'h00000200
`define MINIC_MCR_RX_ERROR_OFFSET 9
`define MINIC_MCR_RX_ERROR 32'h00000200
`define MINIC_MCR_RX_EN_OFFSET 10
`define MINIC_MCR_RX_EN 32'h00000400
`define MINIC_MCR_TX_TS_READY_OFFSET 11
`define MINIC_MCR_TX_TS_READY 32'h00000800
`define MINIC_MCR_RX_EMPTY_OFFSET 12
`define MINIC_MCR_RX_EMPTY 32'h00001000
`define MINIC_MCR_RX_FULL_OFFSET 13
`define MINIC_MCR_RX_FULL 32'h00002000
`define MINIC_MCR_RX_CLASS_OFFSET 16
`define MINIC_MCR_RX_CLASS 32'h00ff0000
`define ADDR_MINIC_TX_ADDR 7'h4
`define ADDR_MINIC_RX_ADDR 7'h8
`define ADDR_MINIC_RX_SIZE 7'hc
`define ADDR_MINIC_RX_AVAIL 7'h10
`define MINIC_MCR_VER_OFFSET 24
`define MINIC_MCR_VER 32'h0f000000
`define ADDR_MINIC_TX_FIFO 7'h4
`define MINIC_TX_FIFO_DAT_OFFSET 0
`define MINIC_TX_FIFO_DAT 32'h0000ffff
`define MINIC_TX_FIFO_TYPE_OFFSET 16
`define MINIC_TX_FIFO_TYPE 32'h00030000
`define ADDR_MINIC_RX_FIFO 7'h8
`define MINIC_RX_FIFO_DAT_OFFSET 0
`define MINIC_RX_FIFO_DAT 32'h0000ffff
`define MINIC_RX_FIFO_TYPE_OFFSET 16
`define MINIC_RX_FIFO_TYPE 32'h00030000
`define MINIC_RX_FIFO_EMPTY_OFFSET 30
`define MINIC_RX_FIFO_EMPTY 32'h40000000
`define MINIC_RX_FIFO_FULL_OFFSET 31
`define MINIC_RX_FIFO_FULL 32'h80000000
`define ADDR_MINIC_RESV_1 7'hc
`define ADDR_MINIC_RESV_2 7'h10
`define ADDR_MINIC_TSR0 7'h14
`define MINIC_TSR0_VALID_OFFSET 0
`define MINIC_TSR0_VALID 32'h00000001
......
sim/wb_packet_sink.svh
View file @ 7d17ce87
......@@ -48,13 +48,18 @@ class WBPacketSink extends EthPacketSink;
pkt.oob_type = TX_FID;
pkt.ts.frame_id = oob & 'hffff;
end
else if (size == 3 && (oob >> 46) == WRF_OOB_RX_TIMESTAMP)
else if (size == 3 && (oob >> 44) == WRF_OOB_RX_TIMESTAMP)
begin
// $display("GotRXOOB");
end else begin
$error("Invalid OOB!");
$stop;
pkt.oob_type = RX_TIMESTAMP;
pkt.ts.port_id = (oob >> 32) & 'h1F;
pkt.ts.ts_f = (oob >> 28) & 'h0F;
pkt.ts.ts_r = oob & 'h0FFFFFFF;
end
else begin
$display("Invalid OOB!");
//$error("Invalid OOB!");
//$stop;
end
......
sim/wb_packet_source.svh
View file @ 7d17ce87
......@@ -43,6 +43,12 @@ class WBPacketSource extends EthPacketSource;
oob[0] = {WRF_OOB_TX_FID, 12'b0};
oob[1] = pkt.ts.frame_id;
end
RX_TIMESTAMP: begin
oob = new[3];
oob[0] = {WRF_OOB_RX_TIMESTAMP, 1'b1, 6'b0, pkt.ts.port_id[4:0]};
oob[1] = {pkt.ts.ts_f, pkt.ts.ts_r[27:16]};
oob[2] = pkt.ts.ts_r[15:0];
end
endcase // case (pkt.oob_type)
return oob;
......
syn/spec_1_1/wr_core_demo/wrc.ram
View file @ 7d17ce87
This diff is collapsed.
testbench/Makefile 0 → 100644
View file @ 7d17ce87
# This Makefile can be called by the Continuous Integration (CI) tool to execute all
# testbenches added for CI
TB_DIRS=wr_minic
TB_DIRS+=wrc_core/main_tb
.PHONY: $(TB_DIRS)
all: $(TB_DIRS)
$(TB_DIRS):
echo $@
@echo "Run HDL-MAKE"
cd "$@"; \
source $(ISE_PATH)/settings64.sh; \
export XILINX=$(ISE_PATH); \
$(HDLMAKE_PATH)/hdl-make 2>&1
@echo "Run make"
$(MAKE) -C $@ $(TARGET)
@echo "Run vsim"
cd "$@"; \
vsim -c -do "run_ci.do"
clean:
for d in $(TB_DIRS); do \
if [ -f $$d/Makefile ]; then \
$(MAKE) -C $$d $@; \
rm -f $$d/Makefile; \
fi \
done
testbench/top_level/Manifest.py
View file @ 7d17ce87
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
include_dirs = [ "../../sim", "gn4124_bfm" ]
files = [ "main.sv" ]
modules = { "local" : [ "../..",
......
testbench/wr_endpoint/full_tb/Manifest.py
View file @ 7d17ce87
target = "xilinx"
action = "simulation"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
files = "main.sv"
fetchto = "../../../ip_cores"
vlog_opt="+incdir+../../../sim +incdir+../../../sim/fabric_emu"
include_dirs = [ "../../../sim" ]
modules ={"git" : [ "git@ohwr.org:hdl-core-lib/general-cores.git" ],
"local" : ["../../../modules/wr_endpoint",
"../../../modules/timing",
......
testbench/wr_fabric_reg/Manifest.py 0 → 100644
View file @ 7d17ce87
action = "simulation"
files = "main.sv"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../ip_cores"
target = "xilinx"
vlog_opt="+incdir+../../sim"
include_dirs = [ "../../sim" ]
modules ={"local" : ["../../",
"../../ip_cores/general-cores",
"../../ip_cores/etherbone-core",
"../../ip_cores/gn4124-core"]}
testbench/wr_minic/Manifest.py
View file @ 7d17ce87
action = "simulation"
files = "main.sv"
#fetchto = "../../ip_cores"
target = "xilinx"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
vlog_opt="+incdir+../../sim"
include_dirs = [ "../../sim" ]
modules ={"local" : ["../../ip_cores/general-cores",
"../../modules/wr_endpoint",
"../../modules/wr_mini_nic" ] };
files = [ "main.sv" ]
modules = { "local" : [ "../../",
"../../ip_cores/general-cores"
]};
testbench/wr_minic/main.sv
View file @ 7d17ce87
This diff is collapsed.
testbench/wr_minic/run.do
View file @ 7d17ce87
......@@ -5,6 +5,7 @@ set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 250us
#run 50ms
run 100ms
wave zoomfull
radix -hexadecimal
testbench/wr_minic/run_ci.do 0 → 100644
View file @ 7d17ce87
# Modelsim run script for continuous integration (with return code)
# execute: vsim -c -do "run_ci.do"
vsim -L unisim -t 10fs work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
run 200ms
#runStatus -full
coverage save coverage.ucdb
quit -code [coverage attribute -name TESTSTATUS -concise]
testbench/wr_minic/wave.do
View file @ 7d17ce87
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/txp_cg_newframe
add wave -noupdate /main/rxp_cg_newframe
add wave -noupdate /main/txp_cg_size
add wave -noupdate /main/rxp_cg_size
add wave -noupdate /main/DUT/g_interface_mode
add wave -noupdate /main/DUT/g_address_granularity
add wave -noupdate /main/DUT/g_memsize_log2
add wave -noupdate /main/DUT/g_buffer_little_endian
add wave -noupdate /main/DUT/clk_sys_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/mem_data_o
add wave -noupdate /main/DUT/mem_addr_o
add wave -noupdate /main/DUT/mem_data_i
add wave -noupdate /main/DUT/mem_wr_o
add wave -noupdate /main/DUT/src_dat_o
add wave -noupdate /main/DUT/src_adr_o
add wave -noupdate /main/DUT/src_sel_o
add wave -noupdate /main/DUT/src_cyc_o
add wave -noupdate /main/DUT/src_stb_o
add wave -noupdate /main/DUT/src_we_o
add wave -noupdate /main/DUT/src_stall_i
add wave -noupdate /main/DUT/src_err_i
add wave -noupdate /main/DUT/src_ack_i
add wave -noupdate /main/DUT/snk_dat_i
add wave -noupdate /main/DUT/snk_adr_i
add wave -noupdate /main/DUT/snk_sel_i
add wave -noupdate /main/DUT/snk_cyc_i
add wave -noupdate /main/DUT/snk_stb_i
add wave -noupdate /main/DUT/snk_we_i
add wave -noupdate /main/DUT/snk_stall_o
add wave -noupdate /main/DUT/snk_err_o
add wave -noupdate /main/DUT/snk_ack_o
add wave -noupdate /main/DUT/txtsu_port_id_i
add wave -noupdate /main/DUT/txtsu_frame_id_i
add wave -noupdate /main/DUT/txtsu_tsval_i
add wave -noupdate /main/DUT/txtsu_valid_i
add wave -noupdate /main/DUT/txtsu_ack_o
add wave -noupdate /main/DUT/wb_cyc_i
add wave -noupdate /main/DUT/wb_stb_i
add wave -noupdate /main/DUT/wb_we_i
add wave -noupdate /main/DUT/wb_sel_i
add wave -noupdate /main/DUT/wb_adr_i
add wave -noupdate /main/DUT/wb_dat_i
add wave -noupdate /main/DUT/wb_dat_o
add wave -noupdate /main/DUT/wb_ack_o
add wave -noupdate /main/DUT/wb_stall_o
add wave -noupdate /main/DUT/wb_irq_o
add wave -noupdate /main/DUT/src_cyc_int
add wave -noupdate /main/DUT/src_stb_int
add wave -noupdate /main/DUT/snk_stall_int
add wave -noupdate /main/DUT/ntx_mem_d
add wave -noupdate /main/DUT/ntx_mem_a
add wave -noupdate /main/DUT/nrx_mem_d
add wave -noupdate /main/DUT/nrx_mux_d
add wave -noupdate /main/DUT/nrx_mem_a
add wave -noupdate /main/DUT/nrx_mem_wr
add wave -noupdate /main/DUT/mem_arb_rx
add wave -noupdate /main/DUT/mem_arb_tx
add wave -noupdate /main/DUT/ntx_status_reg
add wave -noupdate /main/DUT/ntx_data_reg
add wave -noupdate /main/DUT/ntx_cntr_is_zero
add wave -noupdate /main/DUT/ntx_cntr_is_one
add wave -noupdate /main/DUT/ntx_timeout_is_zero
add wave -noupdate /main/DUT/ntx_cntr
add wave -noupdate /main/DUT/ntx_timeout
add wave -noupdate /main/DUT/ntx_ack_count
add wave -noupdate /main/DUT/ntx_has_oob
add wave -noupdate /main/DUT/ntx_state
add wave -noupdate /main/DUT/ntx_start_delayed
add wave -noupdate /main/DUT/ntx_size_odd
add wave -noupdate /main/DUT/ntx_oob_reg
add wave -noupdate /main/DUT/nrx_state
add wave -noupdate /main/DUT/nrx_avail
add wave -noupdate /main/DUT/nrx_toggle
add wave -noupdate /main/DUT/nrx_oob_reg
add wave -noupdate /main/DUT/nrx_status_reg
add wave -noupdate /main/DUT/nrx_error
add wave -noupdate /main/DUT/nrx_mem_a_saved
add wave -noupdate /main/DUT/nrx_has_oob
add wave -noupdate /main/DUT/nrx_bytesel
add wave -noupdate /main/DUT/nrx_size
add wave -noupdate /main/DUT/nrx_rdreg
add wave -noupdate /main/DUT/nrx_buf_full
add wave -noupdate /main/DUT/nrx_stall_mask
add wave -noupdate /main/DUT/nrx_valid
add wave -noupdate /main/DUT/nrx_done
add wave -noupdate /main/DUT/nrx_drop
add wave -noupdate /main/DUT/nrx_stat_error
add wave -noupdate /main/DUT/regs_in
add wave -noupdate /main/DUT/regs_out
add wave -noupdate /main/DUT/wb_in
add wave -noupdate /main/DUT/wb_out
add wave -noupdate /main/DUT/irq_tx
add wave -noupdate /main/DUT/irq_rx_ack
add wave -noupdate /main/DUT/irq_rx
add wave -noupdate /main/DUT/nrx_newpacket
add wave -noupdate /main/DUT/nrx_newpacket_d0
add wave -noupdate /main/DUT/irq_txts
add wave -noupdate /main/DUT/irq_tx_ack
add wave -noupdate /main/DUT/irq_tx_mask
add wave -noupdate /main/DUT/txtsu_ack_int
add wave -noupdate /main/DUT/nrx_status_hp
add wave -noupdate /main/DUT/nrx_status_smac
add wave -noupdate /main/DUT/nrx_status_crc
add wave -noupdate /main/DUT/nrx_status_err
add wave -noupdate /main/DUT/nrx_status_tagme
add wave -noupdate /main/DUT/nrx_status_class
add wave -noupdate /main/DUT/ntx_status_hp
add wave -noupdate /main/DUT/ntx_status_smac
add wave -noupdate /main/DUT/ntx_status_crc
add wave -noupdate /main/DUT/ntx_status_err
add wave -noupdate /main/DUT/ntx_status_tagme
add wave -noupdate /main/DUT/ntx_status_class
add wave -noupdate /main/DUT/ntx_desc_has_src_mac
add wave -noupdate /main/DUT/ntx_desc_802_1q
add wave -noupdate /main/DUT/ntx_desc_with_oob
add wave -noupdate /main/DUT/ntx_desc_valid
add wave -noupdate /main/DUT/ntx_desc_oob
add wave -noupdate /main/DUT/ntx_desc_size
add wave -noupdate -group SRC /main/DUT/src_dat_o
add wave -noupdate -group SRC /main/DUT/src_adr_o
add wave -noupdate -group SRC /main/DUT/src_sel_o
add wave -noupdate -group SRC /main/DUT/src_cyc_o
add wave -noupdate -group SRC /main/DUT/src_stb_o
add wave -noupdate -group SRC /main/DUT/src_we_o
add wave -noupdate -group SRC /main/DUT/src_stall_i
add wave -noupdate -group SRC /main/DUT/src_err_i
add wave -noupdate -group SRC /main/DUT/src_ack_i
add wave -noupdate -expand -group SNK /main/DUT/snk_dat_i
add wave -noupdate -expand -group SNK /main/DUT/snk_adr_i
add wave -noupdate -expand -group SNK /main/DUT/snk_sel_i
add wave -noupdate -expand -group SNK /main/DUT/snk_cyc_i
add wave -noupdate -expand -group SNK /main/DUT/snk_stb_i
add wave -noupdate -expand -group SNK /main/DUT/snk_we_i
add wave -noupdate -expand -group SNK /main/DUT/snk_stall_o
add wave -noupdate -expand -group SNK /main/DUT/snk_err_o
add wave -noupdate -expand -group SNK /main/DUT/snk_ack_o
add wave -noupdate -group TXTSU /main/DUT/txtsu_port_id_i
add wave -noupdate -group TXTSU /main/DUT/txtsu_frame_id_i
add wave -noupdate -group TXTSU /main/DUT/txtsu_tsval_i
add wave -noupdate -group TXTSU /main/DUT/txtsu_ack_o
add wave -noupdate -group WB -expand /main/DUT/wb_out
add wave -noupdate -group WB -expand /main/DUT/wb_in
add wave -noupdate -expand -group TX_PATH -height 16 /main/DUT/ntx_state
add wave -noupdate -expand -group TX_PATH -radix unsigned /main/DUT/ntx_ack_count
add wave -noupdate -expand -group TX_PATH /main/DUT/ntx_flush_last
add wave -noupdate -expand -group TX_PATH /main/DUT/tx_fifo_d
add wave -noupdate -expand -group TX_PATH /main/DUT/tx_fifo_q
add wave -noupdate -expand -group TX_PATH /main/DUT/tx_fifo_we
add wave -noupdate -expand -group TX_PATH /main/DUT/tx_fifo_rd
add wave -noupdate -expand -group TX_PATH /main/DUT/tx_fifo_empty
add wave -noupdate -expand -group TX_PATH /main/DUT/tx_fifo_full
add wave -noupdate -expand -group TX_PATH /main/DUT/txf_ferror
add wave -noupdate -expand -group TX_PATH /main/DUT/txf_fnew
add wave -noupdate -expand -group TX_PATH /main/DUT/txf_data
add wave -noupdate -expand -group TX_PATH /main/DUT/txf_type
add wave -noupdate -expand -group TX_PATH /main/DUT/ntx_stored_dat
add wave -noupdate -expand -group TX_PATH /main/DUT/ntx_stored_type
add wave -noupdate -expand -group TX_PATH /main/DUT/irq_tx
add wave -noupdate -expand -group TX_PATH /main/DUT/irq_tx_ack
add wave -noupdate -expand -group TX_PATH /main/DUT/irq_tx_mask
add wave -noupdate -expand -group TX_PATH /main/DUT/ntx_newpacket
add wave -noupdate -expand -group RX_PATH /main/DUT/regs_out
add wave -noupdate -expand -group RX_PATH -radix unsigned /main/DUT/RX_FIFO/count_o
add wave -noupdate -expand -group RX_PATH -height 16 /main/DUT/nrx_state
add wave -noupdate -expand -group RX_PATH /main/DUT/nrx_sof
add wave -noupdate -expand -group RX_PATH /main/DUT/nrx_eof
add wave -noupdate -expand -group RX_PATH /main/DUT/rxf_data
add wave -noupdate -expand -group RX_PATH /main/DUT/rxf_type
add wave -noupdate -expand -group RX_PATH /main/DUT/rx_fifo_we
add wave -noupdate -expand -group RX_PATH /main/DUT/rx_fifo_q
add wave -noupdate -expand -group RX_PATH /main/DUT/rx_fifo_rd
add wave -noupdate -expand -group RX_PATH /main/DUT/rx_fifo_empty
add wave -noupdate -expand -group RX_PATH /main/DUT/rx_fifo_full
add wave -noupdate -expand -group RX_PATH /main/DUT/rx_fifo_afull
add wave -noupdate -expand -group RX_PATH /main/DUT/irq_rx_ack
add wave -noupdate -expand -group RX_PATH /main/DUT/irq_rx
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {90685000000 fs} 0}
configure wave -namecolwidth 150
WaveRestoreCursors {{Cursor 1} {40485000000 fs} 1} {{Cursor 2} {7845093670430 fs} 0}
configure wave -namecolwidth 208
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
......@@ -131,4 +83,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {90556826170 fs} {90813173830 fs}
WaveRestoreZoom {0 fs} {15051471750 ps}
testbench/wrc_core/main_tb/Manifest.py
View file @ 7d17ce87
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../../ip_cores"
vlog_opt = "+incdir+../../../sim"
files = [ "main.sv" ]
include_dirs = [ "../../../sim" ]
modules = { "local" : [ "../../..",
"../../../modules/fabric",
"../../../ip_cores/general-cores",
"../../../ip_cores/etherbone-core",
"../../../ip_cores/gn4124-core"]}
"../../../ip_cores/gn4124-core" ]}
testbench/wrc_core/main_tb/main.sv
View file @ 7d17ce87
......@@ -99,12 +99,16 @@ module main;
.g_tx_runt_padding(1),
.g_with_external_clock_input(1),
.g_dpram_initf ("sw/wrc.ram"),
.g_dpram_size (131072/4))
.g_dpram_size (131072/4),
.g_diag_id(1),
.g_diag_ver(2),
.g_diag_ro_size(5),
.g_diag_rw_size(1))
DUT (
.clk_sys_i (clk_sys),
.clk_dmtd_i (clk_ref),
.clk_ref_i (clk_ref),
.clk_aux_i (clk_ref),
//.clk_aux_i (clk_ref),
.rst_n_i (rst_n),
.pps_p_o (),
......@@ -178,9 +182,11 @@ module main;
.phy_tx_k_o(phy_tx_k),
.phy_tx_disparity_i(phy_tx_disparity),
.phy_tx_enc_err_i(phy_tx_enc_err),
.phy_rx_data_i(phy_rx_data),
.phy_rx_rbclk_i(clk_ref),
.phy_rx_k_i(phy_rx_k),
//.phy_rx_data_i(phy_rx_data),
//.phy_rx_k_i(phy_rx_k),
.phy_rx_data_i(phy_tx_data),
.phy_rx_k_i(phy_tx_k),
.phy_rx_enc_err_i(phy_rx_enc_err),
.phy_rx_bitslide_i(phy_rx_bitslide),
.phy_rst_o(phy_rst),
......@@ -320,6 +326,7 @@ module main;
initial begin
//CWishboneAccessor acc_wrc;
CSimDrv_WR_Endpoint ep_drv;
uint64_t val;
@(posedge rst_n);
repeat(3) @(posedge clk_sys);
......@@ -349,6 +356,45 @@ module main;
#1400us;
tx_sizes = {};
// acc_wrc.read(`BASE_SYSCON + `ADDR_SYSC_DIAG_INFO, val);
// $display("DIAG ID: %d.%d",
// (val&`SYSC_DIAG_INFO_ID)>>`SYSC_DIAG_INFO_ID_OFFSET, val&`SYSC_DIAG_INFO_VER);
//
// acc_wrc.read(`BASE_SYSCON + `ADDR_SYSC_DIAG_NW, val);
// $display("DIAG out words: %d", val & `SYSC_DIAG_NW_RW);
// $display("DIAG in words: %d", (val & `SYSC_DIAG_NW_RO)>>`SYSC_DIAG_NW_RO_OFFSET);
//
// //reading words
// acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_DIAG_CR, 0);
// acc_wrc.read (`BASE_SYSCON + `ADDR_SYSC_DIAG_DAT, val);
// $display("1st word: %x", val);
//
// acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_DIAG_CR, 1);
// acc_wrc.read (`BASE_SYSCON + `ADDR_SYSC_DIAG_DAT, val);
// $display("2nd word: %x", val);
//
// acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_DIAG_CR, 2);
// acc_wrc.read (`BASE_SYSCON + `ADDR_SYSC_DIAG_DAT, val);
// $display("3rd word: %x", val);
//
// acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_DIAG_CR, 3);
// acc_wrc.read (`BASE_SYSCON + `ADDR_SYSC_DIAG_DAT, val);
// $display("4th word: %x", val);
//
// acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_DIAG_CR, 4);
// acc_wrc.read (`BASE_SYSCON + `ADDR_SYSC_DIAG_DAT, val);
// $display("5th word: %x", val);
//
// acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_DIAG_CR, 5);
// acc_wrc.read (`BASE_SYSCON + `ADDR_SYSC_DIAG_DAT, val);
// $display("6th word: %x", val);
//
// acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_DIAG_DAT, 1);
// acc_wrc.write(`BASE_SYSCON + `ADDR_SYSC_DIAG_CR, `SYSC_DIAG_CR_RW);
// acc_wrc.read (`BASE_SYSCON + `ADDR_SYSC_DIAG_DAT, val);
// $display("next word: %x", val);
//NOW LET'S SEND SOME FRAMES
//send_frames(wrc_src, 3000);
send_frames(ep_src, 20);
......
testbench/wrc_core/main_tb/run_ci.do 0 → 100644
View file @ 7d17ce87
# Modelsim run script for continuous integration (with return code)
# execute: vsim -c -do "run_ci.do"
vsim -L unisim -t 10fs work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
radix -hexadecimal
run 200ms
wave zoomfull
radix -hexadecimal
quit -code [coverage attribute -name TESTSTATUS -concise]
testbench/wrc_core/main_tb/wave.do
View file @ 7d17ce87
This diff is collapsed.
testbench/xwrf_loopback/Manifest.py
View file @ 7d17ce87
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../ip_cores"
vlog_opt = "+incdir+../../sim"
include_dirs = [ "../../sim" ]
files = [ "main.sv" ]
modules = { "local" : [ "../..",
......
testbench/xwrf_mux/Manifest.py
View file @ 7d17ce87
action = "simulation"
target = "xilinx"
files = "main.sv"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
sim_tool = "modelsim"
top_module = "main"
fetchto = "../../ip_cores"
target = "xilinx"
vlog_opt="+incdir+../../sim"
modules ={"local" : "../../" }
include_dirs = [ "../../sim" ]
modules ={"local" : ["../../",
"../../ip_cores/general-cores",
"../../ip_cores/etherbone-core",
"../../ip_cores/gn4124-core"]}
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