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White Rabbit core collection
Commit e4a21ea1 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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modules/wr_endpoint: pulse synchroniser for pfilter_done should use the rx clock reset (input side)

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modules/wr_endpoint/ep_packet_filter.vhd
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......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2014-03-18
-- Last update: 2017-02-02
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -15,7 +15,7 @@
-- constaints are described in detail in the Endpoint's manual.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
-- Copyright (c) 2011-2017 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
......@@ -346,11 +346,8 @@ begin -- behavioral
port map (
clk_in_i => clk_rx_i,
clk_out_i => clk_sys_i,
rst_n_i => rst_n_sys_i,
rst_n_i => rst_n_rx_i,
d_p_i => done_int,
q_p_o => done_o);
end behavioral;
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