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White Rabbit core collection
Commit 264f1d32 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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minic: Rx path rewritten with FIFO

parent e6f4073e
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Showing with 261 additions and 116 deletions
modules/wr_mini_nic/mini_nic.wb
View file @ 264f1d32
......@@ -37,6 +37,26 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "TX_FIFO_EMPTY";
prefix = "TX_EMPTY";
size = 1;
align = 3;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "TX_FIFO_FULL";
prefix = "TX_FULL";
size = 1;
align = 4;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX DMA ready";
prefix = "RX_READY";
......@@ -48,9 +68,9 @@ peripheral {
};
field {
name = "RX DMA buffer full";
prefix = "RX_FULL";
description = "1: RX buffer is full";
name = "RX DMA error";
prefix = "RX_ERROR";
description = "1: RX error, FIFO overflow";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
......@@ -74,6 +94,26 @@ peripheral {
access_dev = WRITE_ONLY;
};
field {
name = "RX_FIFO_EMPTY";
prefix = "RX_EMPTY";
size = 1;
align = 12;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX_FIFO_FULL";
prefix = "RX_FULL";
size = 1;
align = 13;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX Accepted Packet Classes";
prefix = "RX_CLASS";
......@@ -120,25 +160,6 @@ peripheral {
access_dev = READ_ONLY;
};
field {
name = "FIFO_EMPTY";
prefix = "EMPTY";
size = 1;
align = 30;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FIFO_FULL";
prefix = "FULL";
size = 1;
align = 31;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
......@@ -169,7 +190,7 @@ peripheral {
};
field {
name = "FIFO_EMPTY";
name = "RX_FIFO_EMPTY";
prefix = "EMPTY";
size = 1;
align = 30;
......@@ -179,7 +200,7 @@ peripheral {
};
field {
name = "FIFO_FULL";
name = "RX_FIFO_FULL";
prefix = "FULL";
size = 1;
align = 31;
......
modules/wr_mini_nic/minic_wb_slave.vhd
View file @ 264f1d32
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wb_slave.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Fri Oct 21 10:25:03 2016
-- Created : Wed Oct 26 11:30:27 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -130,19 +130,19 @@ begin
rddata_reg(0) <= '0';
rddata_reg(1) <= regs_i.mcr_tx_idle_i;
rddata_reg(2) <= regs_i.mcr_tx_error_i;
rddata_reg(3) <= regs_i.mcr_tx_empty_i;
rddata_reg(4) <= regs_i.mcr_tx_full_i;
rddata_reg(8) <= regs_i.mcr_rx_ready_i;
rddata_reg(9) <= regs_i.mcr_rx_full_i;
rddata_reg(9) <= regs_i.mcr_rx_error_i;
rddata_reg(10) <= minic_mcr_rx_en_int;
rddata_reg(11) <= regs_i.mcr_tx_ts_ready_i;
rddata_reg(12) <= regs_i.mcr_rx_empty_i;
rddata_reg(13) <= regs_i.mcr_rx_full_i;
rddata_reg(23 downto 16) <= minic_mcr_rx_class_int;
rddata_reg(27 downto 24) <= regs_i.mcr_ver_i;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(28) <= 'X';
......@@ -156,8 +156,6 @@ begin
regs_o.tx_fifo_dat_wr_o <= '1';
regs_o.tx_fifo_type_wr_o <= '1';
end if;
rddata_reg(30) <= regs_i.tx_fifo_empty_i;
rddata_reg(31) <= regs_i.tx_fifo_full_i;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
......@@ -188,6 +186,8 @@ begin
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "00010" =>
......@@ -508,11 +508,15 @@ begin
-- TX DMA idle
-- TX DMA error
-- TX_FIFO_EMPTY
-- TX_FIFO_FULL
-- RX DMA ready
-- RX DMA buffer full
-- RX DMA error
-- RX DMA enable
regs_o.mcr_rx_en_o <= minic_mcr_rx_en_int;
-- TX TS ready
-- RX_FIFO_EMPTY
-- RX_FIFO_FULL
-- RX Accepted Packet Classes
regs_o.mcr_rx_class_o <= minic_mcr_rx_class_int;
-- Regs map version
......@@ -522,12 +526,10 @@ begin
-- Data type
-- pass-through field: Data type in register: TX FIFO Register
regs_o.tx_fifo_type_o <= wrdata_reg(17 downto 16);
-- FIFO_EMPTY
-- FIFO_FULL
-- Data to send
-- Data type
-- FIFO_EMPTY
-- FIFO_FULL
-- RX_FIFO_EMPTY
-- RX_FIFO_FULL
-- Timestamp valid
-- Port ID
-- Frame ID
......
modules/wr_mini_nic/minic_wbgen2_pkg.vhd
View file @ 264f1d32
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : minic_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from mini_nic.wb
-- Created : Fri Oct 21 10:25:03 2016
-- Created : Wed Oct 26 11:30:27 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE mini_nic.wb
......@@ -23,12 +23,14 @@ package minic_wbgen2_pkg is
type t_minic_in_registers is record
mcr_tx_idle_i : std_logic;
mcr_tx_error_i : std_logic;
mcr_tx_empty_i : std_logic;
mcr_tx_full_i : std_logic;
mcr_rx_ready_i : std_logic;
mcr_rx_full_i : std_logic;
mcr_rx_error_i : std_logic;
mcr_tx_ts_ready_i : std_logic;
mcr_rx_empty_i : std_logic;
mcr_rx_full_i : std_logic;
mcr_ver_i : std_logic_vector(3 downto 0);
tx_fifo_empty_i : std_logic;
tx_fifo_full_i : std_logic;
rx_fifo_dat_i : std_logic_vector(15 downto 0);
rx_fifo_type_i : std_logic_vector(1 downto 0);
rx_fifo_empty_i : std_logic;
......@@ -44,12 +46,14 @@ package minic_wbgen2_pkg is
constant c_minic_in_registers_init_value: t_minic_in_registers := (
mcr_tx_idle_i => '0',
mcr_tx_error_i => '0',
mcr_tx_empty_i => '0',
mcr_tx_full_i => '0',
mcr_rx_ready_i => '0',
mcr_rx_full_i => '0',
mcr_rx_error_i => '0',
mcr_tx_ts_ready_i => '0',
mcr_rx_empty_i => '0',
mcr_rx_full_i => '0',
mcr_ver_i => (others => '0'),
tx_fifo_empty_i => '0',
tx_fifo_full_i => '0',
rx_fifo_dat_i => (others => '0'),
rx_fifo_type_i => (others => '0'),
rx_fifo_empty_i => '0',
......@@ -118,12 +122,14 @@ variable tmp: t_minic_in_registers;
begin
tmp.mcr_tx_idle_i := f_x_to_zero(left.mcr_tx_idle_i) or f_x_to_zero(right.mcr_tx_idle_i);
tmp.mcr_tx_error_i := f_x_to_zero(left.mcr_tx_error_i) or f_x_to_zero(right.mcr_tx_error_i);
tmp.mcr_tx_empty_i := f_x_to_zero(left.mcr_tx_empty_i) or f_x_to_zero(right.mcr_tx_empty_i);
tmp.mcr_tx_full_i := f_x_to_zero(left.mcr_tx_full_i) or f_x_to_zero(right.mcr_tx_full_i);
tmp.mcr_rx_ready_i := f_x_to_zero(left.mcr_rx_ready_i) or f_x_to_zero(right.mcr_rx_ready_i);
tmp.mcr_rx_full_i := f_x_to_zero(left.mcr_rx_full_i) or f_x_to_zero(right.mcr_rx_full_i);
tmp.mcr_rx_error_i := f_x_to_zero(left.mcr_rx_error_i) or f_x_to_zero(right.mcr_rx_error_i);
tmp.mcr_tx_ts_ready_i := f_x_to_zero(left.mcr_tx_ts_ready_i) or f_x_to_zero(right.mcr_tx_ts_ready_i);
tmp.mcr_rx_empty_i := f_x_to_zero(left.mcr_rx_empty_i) or f_x_to_zero(right.mcr_rx_empty_i);
tmp.mcr_rx_full_i := f_x_to_zero(left.mcr_rx_full_i) or f_x_to_zero(right.mcr_rx_full_i);
tmp.mcr_ver_i := f_x_to_zero(left.mcr_ver_i) or f_x_to_zero(right.mcr_ver_i);
tmp.tx_fifo_empty_i := f_x_to_zero(left.tx_fifo_empty_i) or f_x_to_zero(right.tx_fifo_empty_i);
tmp.tx_fifo_full_i := f_x_to_zero(left.tx_fifo_full_i) or f_x_to_zero(right.tx_fifo_full_i);
tmp.rx_fifo_dat_i := f_x_to_zero(left.rx_fifo_dat_i) or f_x_to_zero(right.rx_fifo_dat_i);
tmp.rx_fifo_type_i := f_x_to_zero(left.rx_fifo_type_i) or f_x_to_zero(right.rx_fifo_type_i);
tmp.rx_fifo_empty_i := f_x_to_zero(left.rx_fifo_empty_i) or f_x_to_zero(right.rx_fifo_empty_i);
......
modules/wr_mini_nic/wr_mini_nic.vhd
View file @ 264f1d32
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