- 14 Jun, 2019 1 commit
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Tomasz Wlostowski authored
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- 13 Jun, 2019 2 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 12 Jun, 2019 1 commit
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Tomasz Wlostowski authored
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- 06 Jun, 2019 1 commit
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Tomasz Wlostowski authored
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- 31 May, 2019 1 commit
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Tomasz Wlostowski authored
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- 25 May, 2019 3 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 29 Mar, 2019 6 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 26 Feb, 2019 1 commit
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Tomasz Wlostowski authored
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- 28 Jan, 2019 1 commit
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Tomasz Wlostowski authored
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- 22 Jan, 2019 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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li hongming authored
The UG382 of Spartan-6 says that the PLLIN of BUFPLL should come from PLL (CLKOUT0/1) or BUFG. "Banks 1, 3, 4, and 5 can optionally be driven by a BUFG (O) when using ENABLE_SYNC (FALSE)." I've tried to modify the setting of ENABLE_SYNC for oserdes_4_to_1/bufpll, but the 10MHz output is still missing. So I have to change the setting of "cmp_sys_clk_pll" to make the 500MHz come from CLKOUT1 and clk_ref come from CLKOUT2.
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- 21 Jan, 2019 20 commits
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li hongming authored
change the function of LEDs: the front end LEDs display the status of link and sync. the on-board LEDS display the act of link and PPS.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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li hongming authored
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li hongming authored
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Grzegorz Daniluk authored
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li hongming authored
Solve compile bug in ucf file.
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li hongming authored
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li hongming authored
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li hongming authored
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li hongming authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Vraliens authored
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Vraliens authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
This reverts commit 21c67bc8. DCM is much more jittery than PLL_BASE: DCM_SP: 125MHz -> 62.5MHz: pk-to-pk jitter: 300ps 125MHz -> 125MHz: pk-to-pk jitter: 200ps 20MHz -> 62.5MHz: pk-to-pk jitter: 1772ps (!!!!) PLL_BASE: 125MHz -> 62.5MHz: pk-to-pk jitter: 185ps 125MHz-> 125MHz: pk-to-pk jitter 161ps 20MHz -> 62.5MHz: pk-to-pk jitter 417ps
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