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White Rabbit core collection
Commit 72f36d2b authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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cute_ref_design: use tm_time_valid instead of new pps_valid output for 10MHz alignment

parent 4c481218
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Showing with 8 additions and 15 deletions
board/cute/wr_cute_pkg.vhd
View file @ 72f36d2b
......@@ -170,7 +170,6 @@ package wr_cute_pkg is
led_link_o : out std_logic;
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
pps_valid_o : out std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o : out std_logic;
......
board/cute/xwrc_board_cute.vhd
View file @ 72f36d2b
......@@ -272,7 +272,6 @@ entity xwrc_board_cute is
btn1_i : in std_logic := '1';
btn2_i : in std_logic := '1';
-- 1PPS output
pps_valid_o: out std_logic;
pps_p_o : out std_logic;
pps_led_o : out std_logic;
pps_csync_o: out std_logic;
......@@ -670,7 +669,6 @@ begin -- architecture struct
link_ok_o => link_ok_o);
tm_time_valid_o <= tm_time_valid;
pps_valid_o <= tm_time_valid;
pll_locked_o <= pll_locked;
onewire_oen_o <= onewire_en(0);
......
top/cute_ref_design/cute_core_ref_top.vhd
View file @ 72f36d2b
......@@ -197,7 +197,6 @@ architecture rtl of cute_core_ref_top is
signal aux_half_high: unsigned(15 downto 0);
signal aux_half_low : unsigned(15 downto 0);
signal aux_shift : unsigned(15 downto 0);
signal pps_valid_d : std_logic;
signal clk_realign : std_logic;
signal new_freq : std_logic;
......@@ -205,9 +204,9 @@ architecture rtl of cute_core_ref_top is
signal pps_csync : std_logic;
attribute maxdelay : string;
attribute maxdelay of pps_csync : signal is "500 ps";
signal pps_valid : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_tai_valid : std_logic;
signal tm_tai_valid_d1 : std_logic;
-- Wishbone buse(s) from masters attached to crossbar
signal cnx_master_out : t_wishbone_master_out_array(0 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(0 downto 0);
......@@ -312,7 +311,6 @@ begin
led_link_o => sfp1_led,
pps_p_o => pps_out,
pps_led_o => usr_led1,
pps_valid_o => pps_valid,
pps_csync_o => pps_csync,
pll_locked_o => pll_locked,
link_ok_o => usr_led2);
......@@ -331,13 +329,13 @@ begin
begin
if rising_edge(clk_ref_125m) then
if(rst_ref_125m_n = '0' or pll_locked = '0') then -- if new_freq or pll lost lock,
pps_valid_d <= '0';
tm_tai_valid_d1 <= '0';
elsif(pps_csync = '1') then
pps_valid_d <= pps_valid;
tm_tai_valid_d1 <= tm_tai_valid;
end if;
end if;
end process;
clk_realign <= (not pps_valid_d) and pps_valid and pps_csync;
clk_realign <= (not tm_tai_valid_d1) and tm_tai_valid and pps_csync;
process(clk_ref_125m)
variable rest : integer range 0 to 65535;
......
top/cute_ref_design/cute_wr_ref_top.vhd
View file @ 72f36d2b
......@@ -190,7 +190,6 @@ architecture rtl of cute_wr_ref_top is
signal aux_half_high: unsigned(15 downto 0);
signal aux_half_low : unsigned(15 downto 0);
signal aux_shift : unsigned(15 downto 0);
signal pps_valid_d : std_logic;
signal clk_realign : std_logic;
signal new_freq : std_logic;
......@@ -218,9 +217,9 @@ architecture rtl of cute_wr_ref_top is
signal pps_csync : std_logic;
attribute maxdelay : string;
attribute maxdelay of pps_csync : signal is "500 ps";
signal pps_valid : std_logic;
signal tm_tai : std_logic_vector(39 downto 0);
signal tm_tai_valid : std_logic;
signal tm_tai_valid_d1 : std_logic;
-- Wishbone buse(s) from masters attached to crossbar
signal cnx_master_out : t_wishbone_master_out_array(0 downto 0);
signal cnx_master_in : t_wishbone_master_in_array(0 downto 0);
......@@ -325,7 +324,6 @@ begin
led_link_o => sfp1_led,
pps_p_o => pps_out,
pps_led_o => usr_led1,
pps_valid_o => pps_valid,
pps_csync_o => pps_csync,
pll_locked_o => pll_locked,
link_ok_o => usr_led2);
......@@ -364,13 +362,13 @@ begin
begin
if rising_edge(clk_ref_125m) then
if(rst_ref_125m_n = '0' or pll_locked = '0') then -- if new_freq or pll lost lock,
pps_valid_d <= '0';
tm_tai_valid_d1 <= '0';
elsif(pps_csync = '1') then
pps_valid_d <= pps_valid;
tm_tai_valid_d1 <= tm_tai_valid;
end if;
end if;
end process;
clk_realign <= (not pps_valid_d) and pps_valid and pps_csync;
clk_realign <= (not tm_tai_valid_d1) and tm_tai_valid and pps_csync;
process(clk_ref_125m)
variable rest : integer range 0 to 65535;
......
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