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White Rabbit core collection
Commit cb11a3d6 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_endpoint/wr_core: independent 8/16-bit PCS data path selection (WIP)

parent 953124a6
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Showing with 131 additions and 96 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ cb11a3d6
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2017-02-20
-- Last update: 2019-06-12
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -183,7 +183,8 @@ package endpoint_pkg is
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_simulation : boolean := false;
g_pcs_16bit : boolean := false;
g_pcs_tx_16bit : boolean := true;
g_pcs_rx_16bit : boolean := true;
g_records_for_phy : boolean := false;
g_tx_force_gap_length : integer := 0;
g_tx_runt_padding : boolean := false;
......@@ -224,15 +225,15 @@ package endpoint_pkg is
phy_debug_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic := '0';
phy_tx_enc_err_i : in std_logic := '0';
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rx_clk_i : in std_logic := '0';
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rx_enc_err_i : in std_logic := '0';
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy8_o : out t_phy_8bits_from_wrc;
phy8_i : in t_phy_8bits_to_wrc := c_dummy_phy8_to_wrc;
phy16_o : out t_phy_16bits_from_wrc;
......@@ -301,7 +302,8 @@ package endpoint_pkg is
g_tx_force_gap_length : integer := 0;
g_tx_runt_padding : boolean := false;
g_simulation : boolean := false;
g_pcs_16bit : boolean := true;
g_pcs_tx_16bit : boolean := true;
g_pcs_rx_16bit : boolean := true;
g_rx_buffer_size : integer := 1024;
g_with_rx_buffer : boolean := true;
g_with_flow_control : boolean := true;
......@@ -339,15 +341,15 @@ package endpoint_pkg is
phy_debug_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rx_clk_i : in std_logic;
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
gmii_tx_clk_i : in std_logic := '0';
gmii_txd_o : out std_logic_vector(7 downto 0) := x"00";
gmii_tx_en_o : out std_logic := '0';
......
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ cb11a3d6
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2017-02-20
-- Last update: 2019-06-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -116,7 +116,8 @@ package endpoint_private_pkg is
component ep_1000basex_pcs
generic (
g_simulation : boolean;
g_16bit : boolean;
g_tx_16bit : boolean;
g_rx_16bit : boolean;
g_ep_idx : integer);
port (
rst_sys_n_i : in std_logic;
......@@ -148,15 +149,15 @@ package endpoint_private_pkg is
serdes_sfp_tx_disable_o : out std_logic;
serdes_rdy_i : in std_logic;
serdes_tx_clk_i : in std_logic;
serdes_tx_data_o : out std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
serdes_tx_k_o : out std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
serdes_tx_data_o : out std_logic_vector(f_pcs_data_width(g_tx_16bit)-1 downto 0);
serdes_tx_k_o : out std_logic_vector(f_pcs_k_width(g_tx_16bit)-1 downto 0);
serdes_tx_disparity_i : in std_logic;
serdes_tx_enc_err_i : in std_logic;
serdes_rx_clk_i : in std_logic;
serdes_rx_data_i : in std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
serdes_rx_k_i : in std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
serdes_rx_data_i : in std_logic_vector(f_pcs_data_width(g_rx_16bit)-1 downto 0);
serdes_rx_k_i : in std_logic_vector(f_pcs_k_width(g_rx_16bit)-1 downto 0);
serdes_rx_enc_err_i : in std_logic;
serdes_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_16bit)-1 downto 0);
serdes_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_rx_16bit)-1 downto 0);
rmon_o : out t_rmon_triggers;
mdio_addr_i : in std_logic_vector(15 downto 0);
mdio_data_i : in std_logic_vector(15 downto 0);
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ cb11a3d6
......@@ -6,7 +6,7 @@
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2019-04-18
-- Last update: 2019-06-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -63,7 +63,9 @@ entity ep_1000basex_pcs is
g_simulation : boolean;
-- PCS datapath width selection: true = 16-bit (Virtex-6), false = 8-bit
-- (Spartan-6 or TBI).
g_16bit : boolean;
g_tx_16bit : boolean;
g_rx_16bit : boolean;
g_ep_idx : integer);
port (
......@@ -161,11 +163,11 @@ entity ep_1000basex_pcs is
-- TX Code group. In 16-bit mode, the MSB is TXed first (tx_data_o[15:8],
-- then tx_data_o[7:0]). In 8-bit mode only bits [7:0] are used.
serdes_tx_data_o : out std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
serdes_tx_data_o : out std_logic_vector(f_pcs_data_width(g_tx_16bit)-1 downto 0);
-- TX Control Code: When 1, a K-character is transmitted. In 16-bit mode,
-- bit 1 goes first, in 8-bit mode only bit 0 is used.
serdes_tx_k_o : out std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
serdes_tx_k_o : out std_logic_vector(f_pcs_k_width(g_tx_16bit)-1 downto 0);
-- TX Disparity input: 1 = last transmitted code group ended with negative
-- running disparity, 0 = positive RD.
......@@ -182,10 +184,10 @@ entity ep_1000basex_pcs is
-- RX recovered clock. MUST be synchronous to incoming serial data stream
-- for proper PTP/SyncE operation. 62.5 MHz in 16-bit mode, 125 MHz in 8-bit mode.
serdes_rx_clk_i : in std_logic;
serdes_rx_data_i : in std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
serdes_rx_k_i : in std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
serdes_rx_data_i : in std_logic_vector(f_pcs_data_width(g_rx_16bit)-1 downto 0);
serdes_rx_k_i : in std_logic_vector(f_pcs_k_width(g_rx_16bit)-1 downto 0);
serdes_rx_enc_err_i : in std_logic;
serdes_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_16bit)-1 downto 0);
serdes_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_rx_16bit)-1 downto 0);
-- RMON events, aligned to clk_sys
rmon_o : out t_rmon_triggers;
......@@ -269,7 +271,7 @@ begin -- rtl
pcs_reset_n <= '0' when (mdio_mcr_reset = '1' or rst_n_i = '0') else '1';
gen_16bit : if(g_16bit) generate
gen_tx_16bit : if(g_tx_16bit) generate
U_TX_PCS : ep_tx_pcs_16bit
port map (
rst_n_i => pcs_reset_n,
......@@ -300,6 +302,10 @@ begin -- rtl
dbg_rd_count_o => dbg_tx_pcs_rd_count_o
);
end generate gen_tx_16bit;
gen_rx_16bit : if g_rx_16bit generate
U_RX_PCS : ep_rx_pcs_16bit
generic map (
g_simulation => g_simulation,
......@@ -346,9 +352,9 @@ begin -- rtl
mdio_wr_spec_bslide <= serdes_rx_bitslide_i(4 downto 0);
end generate gen_16bit;
end generate gen_rx_16bit;
gen_8bit : if(not g_16bit) generate
gen_tx_8bit : if(not g_tx_16bit) generate
U_TX_PCS : ep_tx_pcs_8bit
port map (
rst_n_i => pcs_reset_n,
......@@ -378,6 +384,10 @@ begin -- rtl
preamble_shrinkage => preamble_shrinkage
);
end generate gen_tx_8bit;
gen_rx_8bit: if(not g_rx_16bit) generate
U_RX_PCS : ep_rx_pcs_8bit
generic map (
g_simulation => g_simulation)
......@@ -425,7 +435,7 @@ begin -- rtl
dbg_tx_pcs_wr_count_o <= (others => '0');
nice_dbg_o.rx.fsm <= (others => '0');
end generate gen_8bit;
end generate gen_rx_8bit;
txpcs_busy_o <= txpcs_busy_int;
......
modules/wr_endpoint/ep_timestamping_unit.vhd
View file @ cb11a3d6
......@@ -7,7 +7,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2009-06-22
-- Last update: 2017-02-03
-- Last update: 2019-06-12
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -182,7 +182,7 @@ architecture syn of ep_timestamping_unit is
signal valid_rx, valid_tx : std_logic;
signal cal_count : unsigned(5 downto 0);
signal cal_count : unsigned(5 downto 0) := to_unsigned(1, 6);
signal rx_trigger_mask, rx_trigger_a, rx_cal_pulse_a : std_logic;
signal regs_o_tscr_cs_done : std_logic;
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ cb11a3d6
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2018-10-25
-- Last update: 2019-06-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -61,7 +61,8 @@ entity wr_endpoint is
g_tx_force_gap_length : integer := 0;
g_tx_runt_padding : boolean := true;
g_simulation : boolean := false;
g_pcs_16bit : boolean := true;
g_pcs_tx_16bit : boolean := true;
g_pcs_rx_16bit : boolean := true;
g_rx_buffer_size : integer := 1024;
g_with_rx_buffer : boolean := true;
g_with_flow_control : boolean := true;
......@@ -122,16 +123,16 @@ entity wr_endpoint is
phy_debug_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_rx_16bit)-1 downto 0);
phy_rx_clk_i : in std_logic;
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_rx_16bit)-1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_rx_16bit)-1 downto 0);
-------------------------------------------------------------------------------
-- GMII Interface (8-bit)
......@@ -491,7 +492,8 @@ begin
U_PCS_1000BASEX : ep_1000basex_pcs
generic map (
g_simulation => g_simulation,
g_16bit => g_pcs_16bit,
g_tx_16bit => g_pcs_tx_16bit,
g_rx_16bit => g_pcs_rx_16bit,
g_ep_idx => g_ep_idx)
port map (
rst_sys_n_i => rst_sys_n_i,
......@@ -718,7 +720,7 @@ begin
generic map (
g_timestamp_bits_r => 28,
g_timestamp_bits_f => 4,
g_ref_clock_rate => f_pcs_clock_rate(g_pcs_16bit))
g_ref_clock_rate => f_pcs_clock_rate(g_pcs_rx_16bit))
port map (
clk_ref_i => clk_ref_i,
clk_rx_i => phy_rx_clk_i,
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ cb11a3d6
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-04-26
-- Last update: 2018-03-08
-- Last update: 2019-06-12
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
......@@ -51,7 +51,8 @@ entity xwr_endpoint is
g_simulation : boolean := false;
g_tx_force_gap_length : integer := 0;
g_tx_runt_padding : boolean := false;
g_pcs_16bit : boolean := false;
g_pcs_tx_16bit : boolean := false;
g_pcs_rx_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_rx_buffer_size : integer := 1024;
g_with_rx_buffer : boolean := true;
......@@ -114,16 +115,16 @@ entity xwr_endpoint is
phy_debug_o : out std_logic_vector(15 downto 0);
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic := '0';
phy_tx_enc_err_i : in std_logic := '0';
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rx_clk_i : in std_logic := '0';
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rx_enc_err_i : in std_logic := '0';
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
-- 2nd option is to use record-based I/Os
phy8_o : out t_phy_8bits_from_wrc;
......@@ -284,19 +285,19 @@ architecture syn of xwr_endpoint is
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_loopen_vec : std_logic_vector(2 downto 0);
signal phy_tx_data : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
signal phy_tx_k : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal phy_tx_data : std_logic_vector(f_pcs_data_width(g_pcs_tx_16bit)-1 downto 0);
signal phy_tx_k : std_logic_vector(f_pcs_k_width(g_pcs_tx_16bit)-1 downto 0);
signal phy_tx_prbs_sel : std_logic_vector(2 downto 0);
signal sfp_tx_disable : std_logic;
signal phy_tx_clk : std_logic;
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
signal phy_rx_data : std_logic_vector(f_pcs_data_width(g_pcs_rx_16bit)-1 downto 0);
signal phy_rx_clk : std_logic;
signal phy_rx_k : std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
signal phy_rx_k : std_logic_vector(f_pcs_k_width(g_pcs_rx_16bit)-1 downto 0);
signal phy_rx_enc_err : std_logic;
signal phy_rx_bts : std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
signal phy_rx_bts : std_logic_vector(f_pcs_bts_width(g_pcs_rx_16bit)-1 downto 0);
signal phy_rdy : std_logic;
signal sfp_tx_fault : std_logic;
signal sfp_los : std_logic;
......@@ -311,7 +312,8 @@ begin
g_tx_force_gap_length => g_tx_force_gap_length,
g_tx_runt_padding => g_tx_runt_padding,
g_simulation => g_simulation,
g_pcs_16bit => g_pcs_16bit,
g_pcs_tx_16bit => g_pcs_tx_16bit,
g_pcs_rx_16bit => g_pcs_rx_16bit,
g_rx_buffer_size => g_rx_buffer_size,
g_with_rx_buffer => g_with_rx_buffer,
g_with_flow_control => g_with_flow_control,
......@@ -444,7 +446,7 @@ begin
-- Record-based PHY connections, depending on 8/16-bit PCS
GEN_16BIT_IF: if g_pcs_16bit and g_records_for_phy generate
GEN_16BIT_IF_TX: if g_pcs_tx_16bit and g_records_for_phy generate
phy16_o.rst <= phy_rst;
phy16_o.loopen <= phy_loopen;
phy16_o.loopen_vec <= phy_loopen_vec;
......@@ -453,8 +455,10 @@ begin
phy16_o.tx_prbs_sel <= phy_tx_prbs_sel;
phy16_o.sfp_tx_disable <= sfp_tx_disable;
phy16_o.debug <= phy_debug_out;
phy_tx_clk <= phy16_i.ref_clk;
end generate GEN_16BIT_IF_TX;
GEN_16BIT_IF_RX: if g_pcs_rx_16bit and g_records_for_phy generate
phy_tx_disparity <= phy16_i.tx_disparity;
phy_tx_enc_err <= phy16_i.tx_enc_err;
phy_rx_data <= phy16_i.rx_data;
......@@ -476,9 +480,9 @@ begin
phy_loopen_vec_o <= (others => '0');
phy_tx_prbs_sel_o <= (others => '0');
phy_sfp_tx_disable_o <= '0';
end generate;
end generate GEN_16BIT_IF_RX;
GEN_8BIT_IF: if not g_pcs_16bit and g_records_for_phy generate
GEN_8BIT_IF_TX: if not g_pcs_tx_16bit and g_records_for_phy generate
phy8_o.rst <= phy_rst;
phy8_o.loopen <= phy_loopen;
phy8_o.loopen_vec <= phy_loopen_vec;
......@@ -490,6 +494,10 @@ begin
phy_tx_clk <= phy8_i.ref_clk;
phy_tx_disparity <= phy8_i.tx_disparity;
phy_tx_enc_err <= phy8_i.tx_enc_err;
end generate GEN_8BIT_IF_TX;
GEN_8BIT_IF_RX: if not g_pcs_rx_16bit and g_records_for_phy generate
phy_rx_data <= phy8_i.rx_data;
phy_rx_clk <= phy8_i.rx_clk;
phy_rx_k <= phy8_i.rx_k;
......@@ -508,7 +516,7 @@ begin
phy_loopen_vec_o <= (others => '0');
phy_tx_prbs_sel_o <= (others => '0');
phy_sfp_tx_disable_o <= '0';
end generate;
end generate GEN_8BIT_IF_RX;
-- backwards compatibility
GEN_STD_IF: if not g_records_for_phy generate
......
modules/wrc_core/wr_core.vhd
View file @ cb11a3d6
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2019-03-29
-- Last update: 2019-06-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -92,7 +92,8 @@ entity wr_core is
g_softpll_enable_debugger : boolean := false;
g_softpll_use_sampled_ref_clocks : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_pcs_tx_16bit : boolean := false;
g_pcs_rx_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -140,16 +141,16 @@ entity wr_core is
-- PHY I/f
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_rx_16bit)-1 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_rx_16bit)-1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_rx_16bit)-1 downto 0);
phy_rst_o : out std_logic;
phy_rdy_i : in std_logic := '1';
......@@ -524,16 +525,22 @@ begin
-- PHY TX/RX clock selection based on generics
-----------------------------------------------------------------------------
GEN_16BIT_PHY_IF: if g_pcs_16bit and g_records_for_phy generate
phy_rx_clk <= phy16_i.rx_clk;
GEN_16BIT_PHY_IF1: if g_pcs_tx_16bit and g_records_for_phy generate
phy_tx_clk <= phy16_i.ref_clk;
end generate;
GEN_8BIT_PHY_IF: if not g_pcs_16bit and g_records_for_phy generate
phy_rx_clk <= phy8_i.rx_clk;
GEN_16BIT_PHY_IF2: if g_pcs_rx_16bit and g_records_for_phy generate
phy_rx_clk <= phy16_i.rx_clk;
end generate;
GEN_8BIT_PHY_IF1: if not g_pcs_tx_16bit and g_records_for_phy generate
phy_tx_clk <= phy8_i.ref_clk;
end generate;
GEN_8BIT_PHY_IF2: if not g_pcs_rx_16bit and g_records_for_phy generate
phy_rx_clk <= phy8_i.rx_clk;
end generate;
GEN_STD_PHY_IF: if not g_records_for_phy generate
phy_rx_clk <= phy_rx_rbclk_i;
phy_tx_clk <= phy_ref_clk_i;
......@@ -597,7 +604,7 @@ begin
generic map(
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_ref_clock_rate => f_refclk_rate(g_pcs_16bit),
g_ref_clock_rate => f_refclk_rate(g_pcs_rx_16bit),
g_ext_clock_rate => 10000000,
g_with_ext_clock_input => g_with_external_clock_input)
port map(
......@@ -634,14 +641,14 @@ begin
generic map(
g_with_ext_clock_input => g_with_external_clock_input,
g_reverse_dmtds => false,
g_divide_input_by_2 => not g_pcs_16bit,
g_divide_input_by_2 => not g_pcs_rx_16bit,
g_with_debug_fifo => g_softpll_enable_debugger,
g_tag_bits => 22,
g_interface_mode => PIPELINED,
g_address_granularity => BYTE,
g_num_ref_inputs => 1,
g_num_outputs => 1 + g_aux_clks,
g_ref_clock_rate => f_refclk_rate(g_pcs_16bit),
g_ref_clock_rate => f_refclk_rate(g_pcs_rx_16bit),
g_use_sampled_ref_clocks => g_softpll_use_sampled_ref_clocks,
g_ext_clock_rate => 10000000)
port map(
......@@ -723,7 +730,8 @@ begin
g_address_granularity => BYTE,
g_simulation => f_int2bool(g_simulation),
g_tx_runt_padding => g_tx_runt_padding,
g_pcs_16bit => g_pcs_16bit,
g_pcs_rx_16bit => g_pcs_rx_16bit,
g_pcs_tx_16bit => g_pcs_tx_16bit,
g_records_for_phy => g_records_for_phy,
g_rx_buffer_size => g_rx_buffer_size,
g_with_rx_buffer => true,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ cb11a3d6
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-05-11
-- Last update: 2019-03-29
-- Last update: 2019-06-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -380,7 +380,8 @@ package wrcore_pkg is
g_softpll_enable_debugger : boolean := false;
g_softpll_use_sampled_ref_clocks : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_pcs_tx_16bit : boolean := false;
g_pcs_rx_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -407,15 +408,15 @@ package wrcore_pkg is
-- PHY I/f
-----------------------------------------
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic := '0';
phy_tx_enc_err_i : in std_logic := '0';
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rx_rbclk_i : in std_logic := '0';
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rx_enc_err_i : in std_logic := '0';
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rst_o : out std_logic;
phy_rdy_i : in std_logic := '1';
phy_loopen_o : out std_logic;
......@@ -527,7 +528,8 @@ package wrcore_pkg is
g_softpll_enable_debugger : boolean := false;
g_softpll_use_sampled_ref_clocks : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_pcs_tx_16bit : boolean := false;
g_pcs_rx_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -577,16 +579,16 @@ package wrcore_pkg is
-----------------------------------------
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic := '0';
phy_tx_enc_err_i : in std_logic := '0';
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rx_rbclk_i : in std_logic := '0';
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0):= (others=>'0');
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_rx_16bit)-1 downto 0):= (others=>'0');
phy_rx_enc_err_i : in std_logic := '0';
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_rx_16bit)-1 downto 0) := (others=>'0');
phy_rst_o : out std_logic;
phy_rdy_i : in std_logic := '1';
......
modules/wrc_core/xwr_core.vhd
View file @ cb11a3d6
......@@ -6,7 +6,7 @@
-- Author : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2011-02-02
-- Last update: 2019-03-29
-- Last update: 2019-06-12
-- Platform : FPGA-generics
-- Standard : VHDL
-------------------------------------------------------------------------------
......@@ -91,7 +91,8 @@ entity xwr_core is
g_softpll_enable_debugger : boolean := false;
g_softpll_use_sampled_ref_clocks : boolean := false;
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false;
g_pcs_tx_16bit : boolean := false;
g_pcs_rx_16bit : boolean := false;
g_records_for_phy : boolean := false;
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
......@@ -141,17 +142,17 @@ entity xwr_core is
-----------------------------------------
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_tx_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_rx_16bit)-1 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_rbclk_sampled_i : in std_logic;
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_rx_16bit)-1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_rx_16bit)-1 downto 0);
phy_debug_o : out std_logic_vector(15 downto 0);
phy_debug_i : in std_logic_vector(15 downto 0);
......@@ -296,7 +297,8 @@ begin
g_softpll_enable_debugger => g_softpll_enable_debugger,
g_softpll_use_sampled_ref_clocks => g_softpll_use_sampled_ref_clocks,
g_vuart_fifo_size => g_vuart_fifo_size,
g_pcs_16bit => g_pcs_16bit,
g_pcs_tx_16bit => g_pcs_tx_16bit,
g_pcs_rx_16bit => g_pcs_rx_16bit,
g_records_for_phy => g_records_for_phy,
g_diag_id => g_diag_id,
g_diag_ver => g_diag_ver,
......
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