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White Rabbit core collection
Commit ac2ce366 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wr_gtx_phy_kintex7_lp: removed some unused signals

parent 65285c77
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platform/xilinx/wr_gtp_phy/kintex7-lp/wr_gtx_phy_kintex7_lp.vhd
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......@@ -6,7 +6,7 @@
-- Author : Peter Jansweijer, Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2013-04-08
-- Last update: 2019-03-29
-- Last update: 2019-04-18
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -266,8 +266,6 @@ architecture rtl of wr_gtx_phy_kintex7_lp is
signal gtreset : std_logic;
signal everything_ready : std_logic;
signal rx_cdr_rst : std_logic;
signal rx_synced : std_logic;
signal rst_done : std_logic;
signal rst_done_n : std_logic;
......
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