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White Rabbit core collection
Commit 9347bd38 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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platform/xilinx: add use the other 4 outputs of PLL_BASE as user-defined clocks

parent b84246f9
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Showing with 73 additions and 29 deletions
board/spec/wr_spec_pkg.vhd
View file @ 9347bd38
......@@ -41,6 +41,7 @@ use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.wr_xilinx_pkg.all;
use work.streamers_pkg.all;
package wr_spec_pkg is
......@@ -59,7 +60,7 @@ package wr_spec_pkg is
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
g_ddr_clock_divider : integer := 3);
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
......@@ -73,9 +74,9 @@ package wr_spec_pkg is
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
clk_pll_aux_o : out std_logic_vector(3 downto 0);
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
clk_ddr_o : out std_logic;
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic;
......
board/spec/xwrc_board_spec.vhd
View file @ 9347bd38
......@@ -77,9 +77,8 @@ entity xwrc_board_spec is
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0;
-- DDR clock divider setting
g_ddr_clock_divider :integer := 3
-- User-defined PLL_BASE outputs config
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT
);
port (
---------------------------------------------------------------------------
......@@ -106,8 +105,8 @@ entity xwrc_board_spec is
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- Programmable frequency DDR controller clock output (divider set in g_ddr3_clock_divider)
clk_ddr_o : out std_logic;
-- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE
clk_pll_aux_o : out std_logic_vector(3 downto 0);
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
......@@ -273,7 +272,6 @@ architecture struct of xwrc_board_spec is
-- PLLs, clocks
signal clk_pll_62m5 : std_logic;
signal clk_pll_125m : std_logic;
signal clk_pll_ddr : std_logic;
signal clk_pll_dmtd : std_logic;
signal pll_locked : std_logic;
signal clk_10m_ext : std_logic;
......@@ -326,8 +324,8 @@ begin -- architecture struct
g_fpga_family => "spartan6",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_simulation => g_simulation,
g_ddr_clock_divider => g_ddr_clock_divider)
g_aux_pll_cfg => g_aux_pll_cfg,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
clk_10m_ext_i => clk_10m_ext_i,
......@@ -342,10 +340,10 @@ begin -- architecture struct
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_los_i => sfp_los_i,
sfp_tx_disable_o => sfp_tx_disable_o,
clk_pll_aux_o => clk_pll_aux_o,
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_pll_125m,
clk_62m5_dmtd_o => clk_pll_dmtd,
clk_ddr_o => clk_pll_ddr,
pll_locked_o => pll_locked,
clk_10m_ext_o => clk_10m_ext,
phy8_o => phy8_to_wrc,
......@@ -357,7 +355,6 @@ begin -- architecture struct
clk_sys_62m5_o <= clk_pll_62m5;
clk_ref_125m_o <= clk_pll_125m;
clk_ddr_o <= clk_pll_ddr;
-----------------------------------------------------------------------------
-- Reset logic
......
board/svec/wr_svec_pkg.vhd
View file @ 9347bd38
......@@ -41,6 +41,7 @@ use work.wrcore_pkg.all;
use work.wr_fabric_pkg.all;
use work.endpoint_pkg.all;
use work.wr_board_pkg.all;
use work.wr_xilinx_pkg.all;
use work.streamers_pkg.all;
package wr_svec_pkg is
......@@ -58,7 +59,8 @@ package wr_svec_pkg is
g_diag_id : integer := 0;
g_diag_ver : integer := 0;
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0);
g_diag_rw_size : integer := 0;
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT);
port (
areset_n_i : in std_logic;
areset_edge_n_i : in std_logic := '1';
......@@ -72,6 +74,7 @@ package wr_svec_pkg is
pps_ext_i : in std_logic := '0';
clk_sys_62m5_o : out std_logic;
clk_ref_125m_o : out std_logic;
clk_pll_aux_o : out std_logic_vector(3 downto 0);
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
pll20dac_din_o : out std_logic;
......
board/svec/xwrc_board_svec.vhd
View file @ 9347bd38
......@@ -76,7 +76,9 @@ entity xwrc_board_svec is
g_diag_ver : integer := 0;
-- size the generic diag interface
g_diag_ro_size : integer := 0;
g_diag_rw_size : integer := 0
g_diag_rw_size : integer := 0;
-- User-defined PLL_BASE outputs config
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT
);
port (
---------------------------------------------------------------------------
......@@ -103,6 +105,8 @@ entity xwrc_board_svec is
clk_sys_62m5_o : out std_logic;
-- 125MHz ref clock output
clk_ref_125m_o : out std_logic;
-- Configurable (with g_aux_pll_cfg) clock outputs from the main PLL_BASE
clk_pll_aux_o : out std_logic_vector(3 downto 0);
-- active low reset outputs, synchronous to 62m5 and 125m clocks
rst_sys_62m5_n_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
......@@ -320,6 +324,7 @@ begin -- architecture struct
g_fpga_family => "spartan6",
g_with_external_clock_input => g_with_external_clock_input,
g_use_default_plls => TRUE,
g_aux_pll_cfg => g_aux_pll_cfg,
g_simulation => g_simulation)
port map (
areset_n_i => areset_n_i,
......@@ -335,6 +340,7 @@ begin -- architecture struct
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_los_i => sfp_los_i,
sfp_tx_disable_o => sfp_tx_disable_o,
clk_pll_aux_o => clk_pll_aux_o,
clk_62m5_sys_o => clk_pll_62m5,
clk_125m_ref_o => clk_pll_125m,
clk_62m5_dmtd_o => clk_pll_dmtd,
......
platform/xilinx/wr_xilinx_pkg.vhd
View file @ 9347bd38
......@@ -38,16 +38,26 @@ use work.endpoint_pkg.all;
package wr_xilinx_pkg is
-- Configuration of used-defined aux PLL clocks
type t_auxpll_cfg is record
enabled : boolean;
divide : integer;
end record t_auxpll_cfg;
type t_auxpll_cfg_array is array (0 to 3) of t_auxpll_cfg;
constant c_AUXPLL_CFG_DEFAULT : t_auxpll_cfg := (FALSE, 1);
constant c_AUXPLL_CFG_ARRAY_DEFAULT : t_auxpll_cfg_array := (others=>c_AUXPLL_CFG_DEFAULT);
component xwrc_platform_xilinx is
generic (
g_fpga_family : string := "spartan6";
g_with_external_clock_input : boolean := FALSE;
g_use_default_plls : boolean := TRUE;
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT;
g_gtp_enable_ch0 : integer := 0;
g_gtp_enable_ch1 : integer := 1;
g_gtp_mux_enable : boolean := FALSE;
g_simulation : integer := 0;
g_ddr_clock_divider : integer := 3
g_simulation : integer := 0
);
port (
areset_n_i : in std_logic := '1';
......@@ -67,7 +77,6 @@ package wr_xilinx_pkg is
clk_ext_locked_i : in std_logic := '1';
clk_ext_stopped_i : in std_logic := '0';
clk_ext_rst_o : out std_logic;
clk_ddr_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_rxn_i : in std_logic;
......@@ -83,6 +92,8 @@ package wr_xilinx_pkg is
sfp1_tx_fault_i : in std_logic := '0';
sfp1_los_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
clk_pll_aux_o : out std_logic_vector(3 downto 0);
pll_aux_locked_o : out std_logic;
clk_62m5_sys_o : out std_logic;
clk_125m_ref_o : out std_logic;
clk_ref_locked_o : out std_logic;
......
platform/xilinx/xwrc_platform_xilinx.vhd
View file @ 9347bd38
......@@ -60,14 +60,14 @@ entity xwrc_platform_xilinx is
g_with_external_clock_input : boolean := FALSE;
-- Set to FALSE if you want to instantiate your own PLLs
g_use_default_plls : boolean := TRUE;
-- Config for the auxiliary PLL output (for now only used in Spartan-6
g_aux_pll_cfg : t_auxpll_cfg_array := c_AUXPLL_CFG_ARRAY_DEFAULT;
-- Select GTP channel to use
g_gtp_enable_ch0 : integer := 0;
g_gtp_enable_ch1 : integer := 1;
g_gtp_mux_enable : boolean := FALSE;
-- Set to TRUE will speed up some initialization processes
g_simulation : integer := 0;
g_ddr_clock_divider : integer := 3
);
g_simulation : integer := 0);
port (
---------------------------------------------------------------------------
-- Asynchronous reset (active low)
......@@ -136,6 +136,11 @@ entity xwrc_platform_xilinx is
sfp1_los_i : in std_logic := '0';
sfp1_tx_disable_o : out std_logic;
---------------------------------------------------------------------------
--Auxiliary PLL outputs
---------------------------------------------------------------------------
clk_pll_aux_o : out std_logic_vector(3 downto 0);
pll_aux_locked_o : out std_logic;
---------------------------------------------------------------------------
--Interface to WR PTP Core (WRPC)
---------------------------------------------------------------------------
......@@ -144,7 +149,6 @@ entity xwrc_platform_xilinx is
clk_125m_ref_o : out std_logic;
clk_ref_locked_o : out std_logic;
clk_62m5_dmtd_o : out std_logic;
clk_ddr_o : out std_logic;
pll_locked_o : out std_logic;
clk_10m_ext_o : out std_logic;
-- PHY - CH0
......@@ -239,7 +243,7 @@ begin -- architecture rtl
signal clk_dmtd_fb : std_logic;
signal pll_dmtd_locked : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_ddr : std_logic;
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal clk_125m_pllref_buf_int1 : std_logic;
signal clk_125m_pllref_buf_int2 : std_logic;
......@@ -261,16 +265,30 @@ begin -- architecture rtl
CLKOUT1_DIVIDE => 8,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3,
-- Aux user clocks parameters
CLKOUT2_DIVIDE => g_aux_pll_cfg(0).divide,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => g_aux_pll_cfg(1).divide,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DIVIDE => g_aux_pll_cfg(2).divide,
CLKOUT4_PHASE => 0.000,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DIVIDE => g_aux_pll_cfg(3).divide,
CLKOUT5_PHASE => 0.000,
CLKOUT5_DUTY_CYCLE => 0.500,
----
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => clk_sys_fb,
CLKOUT0 => clk_sys,
CLKOUT1 => clk_125m_pllref_buf_int2,
CLKOUT2 => clk_ddr,
CLKOUT2 => clk_pll_aux(0),
CLKOUT3 => clk_pll_aux(1),
CLKOUT4 => clk_pll_aux(2),
CLKOUT5 => clk_pll_aux(3),
LOCKED => pll_sys_locked,
RST => pll_arst,
CLKFBIN => clk_sys_fb,
......@@ -282,11 +300,18 @@ begin -- architecture rtl
O => clk_125m_pllref_buf_int1,
I => clk_125m_pllref_i);
-- DDR PLL global clock buffer
cmp_ddr_clk_buf_o : BUFG
port map (
O => clk_ddr_o,
I => clk_ddr);
-- DDR PLL global clock buffers
gen_auxclk_bufs: for I in 0 to 3 generate
gen_auxclk_enabled: if g_aux_pll_cfg(I).enabled = TRUE generate
cmp_auxclk_bufg : BUFG
port map (
O => clk_pll_aux_o(I),
I => clk_pll_aux(I));
end generate;
gen_auxclk_disabled: if g_aux_pll_cfg(I).enabled = FALSE generate
clk_pll_aux_o(I) <= '0';
end generate;
end generate;
-- System PLL output clock buffer
cmp_clk_sys_buf_o : BUFG
......@@ -303,6 +328,7 @@ begin -- architecture rtl
clk_62m5_sys_o <= clk_sys_out;
clk_125m_ref_o <= clk_125m_pllref_buf;
pll_locked_o <= pll_sys_locked and pll_dmtd_locked;
pll_aux_locked_o <= pll_sys_locked;
clk_ref_locked_o <= '1';
-- DMTD PLL
......
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